George Alexiou

Design of two-dimensional zero phase FIR fan filters via the McClellan transform

The authors present a method for the design of 2-D zero-phase finite-impulse-response (FIR) fan filters with quadrantal symmetry using the McClellan transform. They give conditions that the coefficients of the McClellan transform must satisfy in order to avoid the scaling of the transform. The proposed design method satisfies these conditions. The resulting cut-off isopotential of the design method is shown to have a very small relative absolute deviation from the ideal one. The method is extended to the design of 2-D zero-phase FIR fan filters of general shape. >

Optimal synthesis of differential cascode voltage switch (DCVS) logic circuits using ordered binary decision diagrams (OBDDs)

This paper presents a method for near-optimum synthesis of Differential Cascade Voltage Switch (DCVS) logic circuits using Ordered Binary Decision Diagrams (OBDD). The method presented produces efficient DCVS circuit structures in terms of transistor count which positively affects the circuit area and performance. The proposed method is also very practical because it produces results with short run-times on a design workstation. The paper presents experimental results that demonstrate the use and the efficiency of the proposed DCVS synthesis method. This method is the basis for a CAD tool that allows automatic synthesis of fault secure circuits based on the DCVS technology.

Using future position restriction rules for stabilizing the results of a noise-sensitive indoor localization system

The testing and evaluation of a low cost system capable of estimating the position of a moving target within an extendible indoor area with low error is presented. Based on a recently developed system architecture, which makes use of a noise-sensitive indoor localization system made up of ir sensors, the position estimation error is based on comparing the number of the digital ir patterns received at the moving target with the expected one. To overcome the problem of instant noise that appears despite the effective system shielding, we employ a number of rules that take into consideration the previous position estimations. These rules are based on the fact that the speed of the target is always limited and its track is smooth most of the time. The test for the rules was made by running a series of experiments on the sensors system, and as a result, we verified that the maximum absolute error in the experimental results is approximately equal to the grid node distance. Moreover, the noise restrictions of the system were tested and recognized, allowing direct measurement of relevant parameters.

Low power BIST for Wallace tree-based multipliers

The low power as a feature of a BIST scheme is a significant target due to quality as well as cost related issues. In this paper we examine the testability of multipliers based on Booth encoding and Wallace tree summation of the partial products and we present a methodology for deriving a low power Built In Self Test (BIST) scheme for them. We propose several design rules for designing the Wallace tree in order to be fully testable under the cell fault model. The proposed low power BIST scheme for the derived multipliers is achieved by: (a) introducing suitable Test Pattern Generators (TPG); (b) properly assigning the TPG outputs to the multiplier inputs; and (c) significantly reducing the test set length with respect to earlier schemes; Our results indicate that the total power dissipated during test can be reduced from 64.8% to 72.8%, while the average power per test vector can be reduced from 19.6% to 27.4% and the peak power dissipation can be reduced from 16.8% to 36.0%, depending on the implementation of the basic cells and the size of the multiplier. The test application time is also significantly reduced, while the introduced BIST scheme implementation area is small.

Design and Simulation of NAND Gates Made of Single Electron Devices

In this paper we present NAND gates designed using single electron logic. First the single-electron NAND behaviour is studied and then the energy performance of the circuit is examined. The whole design and simulation is made using a Monte-Carlo based tool. The results proved that the circuits were behaving as NAND gates, while the free energy study of the system and the stability diagram verified the correct functioning of the circuit.

Design, Simulation and Performance Evaluation of a NAND Based Single-electron 2-4 Decoder

In this paper the design and simulation of a single-electron 2-4 decoder based on NAND gates is presented. The simulation was made using a Monte-Carlo based tool. The results confirmed that the circuit was behaving as a 2-4 decoder. The stability plot and the free energy history diagrams offer detailed analysis of the circuit. The results were compared to similar circuits reported in the literature and the advantages and disadvantages of this design were identified.

Design and Implementation of a Reconfigurable, Embedded Real-Time Face Detection System

This paper presents the design and implementation of a real time face detection system on an embedded reconfigurable platform. Our approach to face detection is based on a skin-segmentation algorithm followed by feature extraction and face verification. Our implementation is done on DMV, a reconfigurable platform with novel features targeting real time computer vision applications. DMV is a system on chip based on the combination of a high performance 32-bit SPARC-compliant processor with data-flow processing blocks.

New challenges emerging on the design of VLSI circuits made of MOSFETs using new gate dielectric materials

While Quality Electronic Design issues regarding typical MOSFETs constructed by well established techniques and made of SiO/sub 2/ gate dielectrics are yet to optimised, new issues regarding the implementation of MOSFETs having gates made of high-k dielectric materials other than SiO/sub 2/ are being raised during the last years. Parameters such as the high dielectric constant values, extra oxide charges and process related defects have to be taken into account. In this paper, such issues are addressed. The case replacing commonly used parameters of the MOSFET modelling with new ones that will take into account the presence of a material with different properties than that of SiO/sub 2/ is presented and proposals are made. Moreover, a case study is presented, where a memory device is examined. An overall estimation of the proposed procedure is attempted and further work is proposed.

On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation

Low power dissipation (PD) during testing is emerging as one of the major objectives of a built-in self-test (BIST) designer. In this paper we examine the testability of multipliers based on Booth encoding and Wallace tree summation of the partial products and we present a methodology for deriving a low power BIST scheme for them. We propose several design rules for designing the Wallace tree in order to be fully testable under the cell fault model. The proposed low power BIST scheme for the derived multipliers is achieved by: (a) introducing suitable test pattern generators (TPGs), (b) properly assigning the TPG outputs to the multiplier inputs and (c) significantly reducing the test set length. Results indicate that the total power dissipated, the average power per test vector and the peak PD during testing can be reduced up to 73%, 27% and 36% respectively with respect to earlier schemes, depending on the implementation of the basic cells and the size of the multiplier. The test application time is also significantly reduced, while the introduced BIST scheme implementation area is small.

An extensible, low cost rapid prototyping environment based on a reconfigurable set of FPGAs

Presents the architecture of a system for the rapid prototyping of digital circuits that is based an the Altera FLEX8000 reconfigurable set of FPGAs. The interconnection architecture of the system consists of both fixed lines between adjacent FPGAs and shared lines that are capable of interconnecting more than two devices. The reconfigurable set of devices is placed on a 2D grid. The external interface of the system enables the connection of two or more base modules to construct a larger grid with similar characteristics.