George Dabos

Column Address Selection in Optical RAMs With Positive and Negative Logic Row Access

An optical RAM row access gate followed by a column address selector for wavelength-division-multiplexing (WDM)-formatted words employing a single semiconductor optical amplifier-Mach-Zehnder interferometer (SOA-MZI) is presented. RAM row access is performed by the SOA-MZI that grants random access to a 4-bit WDM-formatted optical word employing multiwavelength cross-phase-modulation (XPM) phenomena, whereas column decoding is carried out in a completely passive way using arrayed waveguide grating. Proof-of-concept experimental verification for both positive and negative logic access is demonstrated for 4 × 10 Gb/s optical words, showing error-free operation with only 0.4-dB-peak-power penalty and requiring a power value of 25 mW/Gb/s.

Optical RAM row access and column decoding for WDM-formatted optical words

We present a multi-wavelength SOA-MZI-based access gate and an AWG-based column decoder that control random access of 4×10Gb/s WDM-formatted words into a 4-bit optical RAM row. Error-free decoding with 0.4dB peak power penalty is presented.

On-Chip Dual-Stream DWDM Eight-Channel-Capable SOI-Based MUX s /DEMUX s With 40-GH z Channel Bandwidth

We demonstrate two 8 × 1 silicon ring resonator (RR)-based multiplexers (MUXs) integrated on the same chip for dual-stream 16-channel multiplexing/ demultiplexing applications. Cascaded second-order RRs equipped with microheaters were integrated on a silicon-on-insulator platform with the radii of MUX1 and MUX2 being ~12 and ~9 μm, respectively. The resonances of the two MUXs were thermooptically tuned in order to achieve 100-GHz channel spacing, revealing a tuning efficiency of 43 and 36 μW/GHz/RR for MUX1 and MUX2, respectively, and 352 mW total power consumption. Lower than 18 dB crosstalk and higher than 40-GHz 3-dB bandwidth was obtained for the tuned channels of the MUXs. The signal integrity when using these devices in multiplexing and demultiplexing operations was evaluated for a 4 × 10 Gb/s non-return-to-zero data stream (i.e., 10 Gb/s line rate) via bit-error-rate measurements, yielding error-free performance with up to 0.2 dB power penalty for all channels. Proofof-concept demonstration for supporting higher data rates was also realized by using three 100-GHz-spaced 25-Gb/s return-to-zero data signals (i.e., 25 Gb/s line rate) for multiplexing and demultiplexing via MUX2, resulting in error-free operation for all channels with lower than 0.3 dB power penalties.

Ultra-low loss fully-etched grating couplers for perfectly vertical coupling compatible with DUV lithography tools

Hybrid integration of VCSELs onto silicon-on-insulator (SOI) substrates has emerged as an attractive approach for bridging the gap between cost-effective and energy-efficient directly modulated laser sources and silicon-based PICs by leveraging flip-chip (FC) bonding techniques and silicon grating couplers (GCs). In this context, silicon GCs, should comply with the process requirements imposed by the complimentary-metal-oxide-semiconductor manufacturing tools addressing in parallel the challenges originating from the perfectly vertical incidence. Firstly, fully etched GCs compatible with deep-ultraviolet lithography tools offering high coupling efficiencies are imperatively needed to maintain low fabrication cost. Secondly, GCs tolerance to VCSEL bonding misalignment errors is a prerequisite for practical deployment. Finally, a major challenge originating from the perfectly vertical coupling scheme is the minimization of the direct back-reflection to the VCSEL’s outgoing facet which may destabilize its operation. Motivated from the above challenges, we used numerical simulation tools to design an ultra-low loss, bidirectional VCSEL-to-SOI optical coupling scheme for either TE or TM polarization, based on low-cost fully etched GCs with a Si-layer of 340 nm without employing bottom reflectors or optimizing the buried-oxide layer. Comprehensive 2D Finite-Difference-Time- Domain simulations have been performed. The reported GC layout remains fully compatible with the back-end-of-line (BEOL) stack associated with the 3D integration technology exploiting all the inter-metal-dielectric (IMD) layers of the CMOS fab. Simulation results predicted for the first time in fully etched structures a coupling efficiency of as low as -0.87 dB at 1548 nm and -1.47 dB at 1560 nm with a minimum direct back-reflection of -27.4 dB and -14.2 dB for TE and TM polarization, respectively.

Low back-reflection CMOS-compatible grating coupler for perfectly vertical coupling

In view of high volume manufacturing of silicon based photonic-integrated-circuits (Si-PICs), CMOS compatible low-cost fabrication processes as well as simplified packaging methods are imperatively needed. Silicon-onInsulator (SOI) based grating couplers (GCs) have attracted attention as the key components for providing optical interfaces to Si-PICs due their fabrication simplicity compared to the edge coupling alternatives. GCs based on perfectly vertical coupling scheme become essential by introducing substantial savings in the packaging cost as no angular configurations are required but at the expense of high coupling efficiency values due to the second order diffraction. In this context, research efforts concentrated on designing GCs with minimized back reflection into the waveguide yet employing more than one etching steps or rather complex fabrication processes. Herein, we propose a fully etched CMOS compatible non-uniform one-dimensional (1D) GC for perfectly vertical coupling with low back reflected optical power by means of numerical simulations. A particle-swarm-optimization (PSO) algorithm was deployed in conjunction with a commercially available 2D finite-difference-time-domain (FDTD) method to maximize the coupling efficiency to a SMF fiber for TM polarization. The design parameters were restricted to the period length and the filling factor while the minimum feature size was 80 nm. A peak coupling loss of 4.4 dB at 1553 nm was achieved with a 1-dB bandwidth of 47 nm and a back reflection of -20 dB. The coupling tolerance to fabrication errors was also investigated.

Cost-effective single-etched TM-mode SOI grating couplers for broadband perfectly vertical coupling

In this paper we present a uniform fully-etched TM-mode grating coupler for vertical coupling of light into SOI photonic integrated circuits and a chirped alternative to increase its bandwidth by using the same fabrication steps and maintaining its coupling efficiency. The first design refers to a uniform grating consisting of 22 periods with 670 nm period length, exhibiting 5.6 dB coupling losses at 1564 nm and a 3dB bandwidth of 32 nm. The 3dB bandwidth is extended from 32 to 76 nm by adding a chirped section at the front end of the uniform section in the second design. The ultra-wideband coupler can be used across all C-band as well as in S and L bands, it is realized at no expense of fabrication complexity while coupling efficiency is maintained. The coupling efficiency can be improved if the grating gap is decreased below 80 nm yet increasing fabrication resolution requirements. Theoretical and experimental analysis is presented for the coupling efficiency versus structure period and gap width while angle alignment tolerance is also investigated.

Aluminum plasmonic waveguides co-integrated with Si 3 N 4 photonics using CMOS processes

Co-integrating CMOS plasmonics and photonics became the “sweet spot” to hit in order to combine their benefits and allow for volume manufacturing of plasmo-photonic integrated circuits. Plasmonics can naturally interface photonics with electronics while offering strong mode confinement, enabling in this way on-chip data interconnects when tailored to single-mode waveguides, as well as high-sensitivity biosensors when exposing Surface-Plasmon-Polariton (SPP) modes in aqueous environment. Their synergy with low-loss photonics can tolerate the high plasmonic propagation losses in interconnect applications, offering at the same time a powerful portfolio of passive photonic functions towards avoiding the use of bulk optics for SPP excitation and facilitating compact biosensor setups. The co-integration roadmap has to proceed, however, over the utilization of fully CMOS compatible material platforms and manufacturing processes in order to allow for a practical deployment route. Herein, we demonstrate for the first time Aluminum plasmonic waveguides co-integrated with Si3N4 photonics using CMOS manufacturing processes. We validate the data carrying credentials of CMOS plasmonics with 25 Gb/s data traffic and we confirm successful plasmonic propagation in both air and water-cladded waveguide configurations. This platform can potentially fuel the deployment of co-integrated plasmonic and photonic structures using CMOS processes for biosensing and on-chip interconnect applications.

CMOS plasmonic waveguides co-integrated with LPCVD-based Si3N4 via a butt-coupled interface

Plasmonic technology has attracted intense research interest enhancing the functional portfolio of photonic integrated circuits (PICs) by providing Surface-Plasmon-Polariton (SPP) modes with ultra-high confinement at sub-wavelength scale dimensions and as such increased light matter interaction. However, in most cases plasmonic waveguides rely mainly on noble metals and exhibit high optical losses, impeding their employment in CMOS processes and their practical deployment in highly useful PICs. Hence, merging CMOS compatible plasmonic waveguides with low-loss photonics by judiciously interfacing these two waveguide platforms appears as the most promising route towards the rapid and costefficient manufacturing of high-performance plasmo-photonic integrated circuits. In this work, we present butt-coupled plasmo-photonic interfaces between CMOS compatible 7μm-wide Aluminum (Al) and Copper (Cu) metal stripes and 360×800nm Si3N4 waveguides. The interfaces have been designed by means of 3D FDTD and have been optimized for aqueous environment targeting their future employment in biosensing interferometric arrangements, with the photonic waveguides being cladded with 660nm of Low Temperature Oxide (LTO) and the plasmonic stripes being recessed in a cavity formed between the photonic waveguides. The geometrical parameters of the interface will be presented based on detailed simulation results, using experimentally verified plasmonic properties for the employed CMOS metals. Numerical simulations dictated a coupling efficiency of 53% and 68% at 1.55μm wavelength for Al and Cu, respectively, with the plasmonic propagation length Lspp equaling 66μm for Al and 75μm for Cu with water considered as the top cladding. The proposed interface configuration is currently being fabricated for experimental verification.

Efficient coupling between Si3N4 photonic and hybrid slot-based CMOS plasmonic waveguide

Bringing photonics and electronics into a common integration platform can unleash unprecedented performance capabilities in data communication and sensing applications. Plasmonics were proposed as the key technology that can merge ultra-fast photonics and low-dimension electronics due to their metallic nature and their unique ability to guide light at sub-wavelength scales. However, inherent high losses of plasmonics in conjunction with the use of CMOS incompatible metals like gold and silver which are broadly utilized in plasmonic applications impede their broad utilization in Photonic Integrated Circuits (PICs). To overcome those limitations and fully exploit the profound benefits of plasmonics, they have to be developed along two technology directives. 1) Selectively co-integrate nanoscale plasmonics with low-loss photonics and 2) replace noble metals with alternative CMOS-compatible counterparts accelerating volume manufacturing of plasmo-photonic ICs. In this context, a hybrid plasmo-photonic structure utilizing the CMOS-compatible metals Aluminum (Al) and Copper (Cu) is proposed to efficiently transfer light between a low-loss Si3N4 photonic waveguide and a hybrid plasmonic slot waveguide. Specifically, a Si3N4 strip waveguide (photonic part) is located below a metallic slot (plasmonic part) forming a hybrid structure. This configuration, if properly designed, can support modes that exhibit quasi even or odd symmetry allowing power exchange between the two parts. According to 3D FDTD simulations, the proposed directional coupling scheme can achieve coupling efficiencies at 1550nm up to 60% and 74% in the case of Al and Cu respectively within a coupling length of just several microns.

Low-cost vertical coupling schemes for optical I/Os and 3D integration in CMOS photonic integrated circuits

Grating coupler structures have attracted prominent research and development efforts to address off-chip, vertical light coupling for wafer-level test and complex optical assemblies. In fact, three-dimensional (3D) integration is introduced as the key enabling technology for low footprint, high frequency and low loss silicon photonic and opto-electronic integrated circuits. Towards this direction, low-cost and CMOS compatible fabrication processes are required for the cost-effective mass-manufacturing of silicon photonic devices by CMOS foundries. This paper presents the recent research outcomes on effective perfectly normal grating couplers designed and fabricated on 340 nm thick silicon-on-insulator (SOI) following low cost methodologies that comply with CMOS fabrication processes while minimizing lithography and etching steps.