N. Pleros

A 320 Gb/s-Throughput Capable 2

We demonstrate a 2 × 2 silicon-plasmonic router architecture with 320 Gb/s throughput capabilities for optical interconnect applications. The proposed router platform relies on a novel dual-ring Dielectric-Loaded Surface Plasmon Polariton (DLSPP) 2 × 2 switch heterointegrated on a Silicon-on-Insulator (SOI) photonic motherboard that is responsible for traffic multiplexing and header processing functionalities. We present experimental results of a Poly-methyl-methacrylate (PMMA)-loaded dual-resonator DLSPP waveguide structure that uses two racetrack resonators of 5.5 μm radius and 4 μ m-long straight sections and operates as a passive add/drop filtering element. We derive its frequency-domain transfer function, confirm its add/drop experimental spectral response, and proceed to a circuit-level model for dual-ring DLSPP designs supporting 2 × 2 thermo-optic switch operation. The validity of our circuit-level modeled 2 × 2 thermo-optic switch is verified by means of respective full vectorial three-dimensional Finite Element Method (3D-FEM) simulations. The router setup is completed by means of two 4 × 1 SOI multiplexing circuits, each one employing four cascaded second order micro-ring configurations with 100 GHz spaced resonances. Successful interconnection between the DLSPP switching matrix and the SOI circuitry is performed through a butt-coupling design that, as shown via 3D-FEM analysis, allows for small coupling losses of as low as 2.6 dB. The final router architecture is evaluated through a co-operative simulation environment, demonstrating successful 2 × 2 routing for two incoming 4-wavelength Non-Return-to-Zero (NRZ) optical packet streams with 40 Gb/s line-rates.

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We demonstrate for the first time a 40 Gb/s all-optical 3R burst-mode receiver error-free operation for 9,3 dB power fluctuation between short bursty packets. It consists of a sequence of four integrated MZI switches.

2 Silicon-Plasmonic Router Architecture for Optical Interconnects

The thermo-optical dynamics of polymer loaded surface plasmon waveguide (PLSPPW) based devices photo-thermally excited in the nanosecond regime is investigated. We demonstrate thermo-absorption of PLSPPW modes mediated by the temperature-dependent ohmic losses of the metal and the thermally controlled field distribution of the plasmon mode within the metal. For a PLSPPW excited by sub-nanosecond long pulses, we find that the thermo-absorption process leads to modulation depths up to 50% and features an activation time around 2 ns whereas the relaxation time is around 800 ns, four-fold smaller than the cooling time of the metal film itself. Next, we observe the photo-thermal activation of PLSPPW racetrack shaped resonators at a time scale of 300 ns followed however by a long cooling time (18 μs) attributed to the poor heat diffusivity of the polymer. We conclude that nanosecond excitation combined to high thermal diffusivity materials opens the way to high speed thermo-optical plasmonic devices.

A 40 Gb/s 3R Burst Mode Receiver with 4 integrated MZI switches

We present a novel scheme for high-speed multiwavelength clock recovery using a low finesse Fabry-Perot filter and a quantum-dot semiconductor optical amplifier. Performance evaluation based on extensive numerical analysis reveals that the proposed configuration can acquire clock from 40- and 160-Gb/s input data packet streams at four wavelengths with very short rise- and fall-times.

Nanosecond thermo-optical dynamics of polymer loaded plasmonic waveguides

We report the first experimental performance evaluation of a 75-μm-long plasmonic multimode interference switch that is hetero-integrated on a silicon-on-insulator platform, operating with 10-Gb/s data signals. The switch exhibits a 2.9-μs response time and 44.5% modulation depth, while the extinction ratio between the ports alters from 5.4 to -1.5 dB for 35-mW electrical (switching) power. Error-free performance was achieved.

A High-Speed Multiwavelength Clock Recovery Scheme for Optical Packets

We present a 3-bit all-optical counter comprising two cascaded stages of a novel optical T-Flip-Flop that employs one SOA-MZI and a feedback loop. Experimental verification is demonstrated at 8MHz using a fiber-based feedback loop implementation.

Demonstration of a Plasmonic MMI Switch in 10-Gb/s True Data Traffic Conditions

We demonstrate a novel Medium-Transparent MAC (MT-MAC) protocol with enhanced end-user service delivery fairness properties for use in Gbps capable, 60 GHz Fiber- Wireless (FiWi) LAN networks. Our approach relies on incorporating a Client Weighted Algorithm (CWA) in the optical capacity allocation mechanism employed in the MT-MAC scheme, so as to distribute the available wavelengths to the different antenna units according to the total number of active users served by each individual antenna. The protocols throughput fairness characteristics are confirmed through extensive simulations for different end-users distributions, varying traffic loads and multiple optical wavelength availabilities at 1 Gbps data rates. The presented results show that complete throughput and delay equalization can be achieved even for highly varying user population patterns among the different antenna units when certain wavelength availability conditions are satisfied. The performance of the proposed protocol has been compared with respective results obtained by the state-of-the-art MT-MAC scheme where a round-robin arbitration algorithm is used, clearly confirming the increased fairness capabilities of our approach. In addition, the proposed scheme is simple and remains clearly distinct from the wireless capacity arbitration process, highlighting in this way the high-level agility and flexibility of the MT-MAC platform for use in high-speed 60 GHz FiWi LANs.

All-optical 3-bit counter using two cascaded stages of SOA-MZI-based T-flip-flops

Towards Single Mode Fiber (SMF) based optical connections in Data Centers (DCs) we are presenting the SM platform of the EU FP7 project PhoxTror. The major building blocks envisioned in this area are a 3D transceiver with a capacity of up to 480 Gb/s and a 3D router with 480 Gb/s throughput based on a Si photonics switching matrix. Towards this goal it is presented the basic 2×2 switching elements, the 4×4 switching matrix of the router and the Optical Through Silicon Vias (OTSVs) that enable the 3D functionality in the Si interposer.

Throughput and delay fairness through an agile medium-transparent MAC protocol for 60GHz fiber-wireless LAN networks

Hybrid integration of VCSELs onto silicon-on-insulator (SOI) substrates has emerged as an attractive approach for bridging the gap between cost-effective and energy-efficient directly modulated laser sources and silicon-based PICs by leveraging flip-chip (FC) bonding techniques and silicon grating couplers (GCs). In this context, silicon GCs, should comply with the process requirements imposed by the complimentary-metal-oxide-semiconductor manufacturing tools addressing in parallel the challenges originating from the perfectly vertical incidence. Firstly, fully etched GCs compatible with deep-ultraviolet lithography tools offering high coupling efficiencies are imperatively needed to maintain low fabrication cost. Secondly, GCs tolerance to VCSEL bonding misalignment errors is a prerequisite for practical deployment. Finally, a major challenge originating from the perfectly vertical coupling scheme is the minimization of the direct back-reflection to the VCSEL’s outgoing facet which may destabilize its operation. Motivated from the above challenges, we used numerical simulation tools to design an ultra-low loss, bidirectional VCSEL-to-SOI optical coupling scheme for either TE or TM polarization, based on low-cost fully etched GCs with a Si-layer of 340 nm without employing bottom reflectors or optimizing the buried-oxide layer. Comprehensive 2D Finite-Difference-Time- Domain simulations have been performed. The reported GC layout remains fully compatible with the back-end-of-line (BEOL) stack associated with the 3D integration technology exploiting all the inter-metal-dielectric (IMD) layers of the CMOS fab. Simulation results predicted for the first time in fully etched structures a coupling efficiency of as low as -0.87 dB at 1548 nm and -1.47 dB at 1560 nm with a minimum direct back-reflection of -27.4 dB and -14.2 dB for TE and TM polarization, respectively.

Single Mode Optical Interconnects for future data centers

At the dawning of the exaflop era, High Performance Computers are foreseen to exploit integrated all-optical elements, to overcome the speed limitations imposed by electronic counterparts. Drawing from the well-known Memory Wall limitation, imposing a performance gap between processor and memory speeds, research has focused on developing ultra-fast latching devices and all-optical memory elements capable of delivering buffering and switching functionalities at unprecedented bit-rates. Following the master-slave configuration of electronic Flip-Flops, coupled SOA-MZI based switches have been theoretically investigated to exceed 40 Gb/s operation, provided a short coupling waveguide. However, this flip-flop architecture has been only hybridly integrated with silica-on-silicon integration technology exhibiting a total footprint of 45x12 mm2 and intra-Flip-Flop coupling waveguide of 2.5cm, limited at 5 Gb/s operation. Monolithic integration offers the possibility to fabricate multiple active and passive photonic components on a single chip at a close proximity towards, bearing promises for fast all-optical memories. Here, we present for the first time a monolithically integrated all-optical SR Flip-Flop with coupled master-slave SOA-MZI switches. The photonic chip is integrated on a 6x2 mm2 die as a part of a multi-project wafer run using library based components of a generic InP platform, fiber-pigtailed and fully packaged on a temperature controlled ceramic submount module with electrical contacts. The intra Flip-Flop coupling waveguide is 5 mm long, reducing the total footprint by two orders of magnitude. Successful flip flop functionality is evaluated at 10 Gb/s with clear open eye diagram, achieving error free operation with a power penalty of 4dB.