George L. Brantingham

Parameter interpolator for speech synthesis circuit

Disclosed is a parameter interpolator for a speech synthesis circuit. Using a parameter interpolator permits the data rate to the speech synthesis circuit to be lowered inasmuch as the incoming speech data is used to slowly charge the data previously inputted to the values of the incoming data. The speech synthesis circuit includes an input circuit for receiving the target values of the speech data and a memory for stored interpolated values of the speech data. The interpolator includes a circuit coupled to the input circuit and the memory which calculates the difference between the target values and the stored values. Another circuit is used to add a portion of the difference to the values stored in the memory; the particular portion of the difference is equal to 1/2N where N=0, 1, 2 . . . Further, the interpolator is arranged to inhibit the normal interpolation upon certain conditions, such as changes from voiced speech to unvoiced speech, and visa versa.

System using digital filter for waveform or speech synthesis

A system using a digital filter for generating complex waveforms, such as human speech. The filter has a multiplier, an adder coupled to the output of the multiplier and various delay circuits coupled to the output of the adder. A latch memory is coupled to the output of one of the delay circuits. Switching circuits are provided for the output of the delay and the latch memory to inputs of the multiplier and the adder to selected times. Coefficients of the filter are preferably stored in a memory coupled to another input of the multiplier. The excitation signal is coupled to the adder in one embodiment and to the multiplier in another embodiment.

Electronic handheld translator having miniature electronic speech synthesis chip

An electronic handheld talking translator including a speech synthesis integrated circuit device. The speech synthesis integrated circuit device includes a digital filter, a voiced/unvoiced excitation circuit, a speech parameter interpolator, an input parameter decoder, a digital-to-analog converter, a speaker and associated timing circuits. A non-volatile memory stores digital data representative of the correct spellings of selected words in a foreign language and the model vocal tract control data necessary to control the speech synthesis circuit in a manner to cause the selected words to be audibly pronounced by the translator.

Text-To-Speech Using LPC Allophone Stringing

A low cost voice response system is presented, which performs text-to-speech conversion of any English text. The system is built around an LPC synthesizer chip and a microprocessor. Text-to-allophone rules are used to convert an input string of ASCII characters into allophonic codes. LPC parameters are then drawn from an allophone library, which takes very little storage space, and concatenated using a fast and simple algorithm to produce natural sounding speech.

Variable frame length data converter for a speech synthesis circuit

A speech synthesis circuit is provided with a variable frame length data converter and the speech synthesizer is preferably integrated on an integrated circuit chips. The variable frame length data converter reduces the amount of data required to synthesizer human speech at a given quality level. Preferably, a full frame of data includes, a pitch parameter, an energy parameter, a repeat bit and a plurality of speech coefficients. Each parameter or coefficient has a preselected length, but each frame has a variable number of parameters or coefficients associated therewith. The parameters and coefficients are encoded and a particular code of the pitch parameter indicates that the speech is to be unvoiced. An unvoiced frame includes fewer coefficients that a voiced frame and the converter detects this particular pitch parameter and automatically sets the unsent coefficients to zero. The converter also detects the state of the repeat bit for controlling the synthesizing to use the coefficients received during the previous frame as the coefficient to be used to generate speech in response to the present frame. In this embodiment, when the repeat bit comes up, new pitch and energy parameters are inputted therewith. Further, the converters preferably detects particular codes in the energy parameter for determining when a pause occurs or when the last frame of data has been sent.

Synchronous method and apparatus for speech synthesis circuit

A speech synthesis circuit capable of being implemented in an integrated circuit is disclosed. The speech synthesis circuit has an input port for receiving frames of data consisting of speech coefficients, a memory for storing interpolated values of the speech coefficients and an interpolator circuit coupled to the input port and to the memory. A synchronous timing circuit is provided for generating a data frame timing signal, interpolation count timing signals and parameter count timing signals. The rate of the parameter count timing signals is a multiple of the rate of the interpolation count timing signals, which is in turn a multiple of the rate of the data frame timing signal. These signals occur at predetermined times and are generated in the disclosed embodiment by Programmed Logic Arrays (PLAs). The data frame timing signal controls the receipt of a new frame of data at the input port. The interpolation count timing signal controls the initiation of a sequence of interpolations by the interpolator circuit between the values of the speech coefficients of the previous frame of data, and the values of the speech coefficients contained in the current frame. The parameter count timing signals are utilized to control when each coefficient is received at the input port after a data frame timing signal has occurred and also control the transferring of particular speech parameters to the interpolator circuit from the memory.

Speech synthesis system with parameter look up table

This system includes an LPC parameter speech synthesizer which basically needs ten binary bits for each LPC coefficient. However, external sources are allowed reduced storage and frame rate requirements by encoding the set of LPC coefficients in a data frame with bit-allocation, repeat-bit, and variable-length features. A three-memory system provides transformation: a speech word selected by controller 11 is transformed by a ROM (30) into an address to a ROM (12 or 13) which outputs corresponding speech data in reduced encoded format to a ROM (202) which converts the coded frame of coefficients to uncoded ten-bit coefficients as needed by the speech synthesizer.

Method and apparatus for speech synthesis filter excitation

A speech synthesis system utilizing a linear predictive filter. Voiced and unvoiced excitations are applied to the filter to produce a digital signal representative of human speech. The voiced excitation is provided by a repeating chirp function stored in memory. The unvoiced excitation consists of two excitation signals of opposite sign, stored in programmable memory and randomly addressed. The programmable storage of unvoiced excitation signals allows gain scaling between voiced and unvoiced excitation to be easily accomplished.