Richard H. Wiggins

Speech synthesis system utilizing variable frame rate

Speech synthesis system implementable in an integrated circuit device capable of converting frames of speech data at a variable frame rate into analog signals representative of human speech. The frames of speech data comprise digital representations of values of pitch, energy, filter coefficients and coded frame rate data. The speech synthesis system includes a linear predictive coding filter as a speech synthesizer which utilizes the speech data at a varying frame rate to produce digital speech signals representative of human speech. Frames of digital speech data including coded frame rate data are received by an input, with the frame rate data being decoded to control both the rate at which the incoming variable-length frames of speech data are accepted by the speech synthesizer and the number of interpolation calculations required to define interpolated speech values between adjacent incoming frames of speech data. A frame control circuit accomplishes the foregoing utilization of speech data at a variable frame rate by the speech synthesizer by providing for a variable number of interpolation calculations between adjacent speech frames from last implemented speech data in which the number of interpolation calculations in a given instance is determined by the frame rate data. A microprocessor controls the access of selected speech data which is stored in a memory. The system also includes a digital-to-analog converter for converting the digital speech signals produced by the filter into analog signals and a speaker for generating audible sounds in the form of synthesized human speech from the analog signals provided by the digital-to-analog converter.

System using digital filter for waveform or speech synthesis

A system using a digital filter for generating complex waveforms, such as human speech. The filter has a multiplier, an adder coupled to the output of the multiplier and various delay circuits coupled to the output of the adder. A latch memory is coupled to the output of one of the delay circuits. Switching circuits are provided for the output of the delay and the latch memory to inputs of the multiplier and the adder to selected times. Coefficients of the filter are preferably stored in a memory coupled to another input of the multiplier. The excitation signal is coupled to the adder in one embodiment and to the multiplier in another embodiment.

Interactive device for teaching musical tones or melodies

An electronic learning aid for interactive operation with an operator with capabilities for the synthesis of a tone or sequence of tones. The tone, in the alternative, is used to either prompt the operator to respond in like fashion or is in response to the operators input of a tone or sequence of tones. In this fashion the learning aid selects a tune to be synthesized and communicates this tonal sequence to the operator who responds by attempting to mimic the sequence. An alternate operation of the learning aid is for the operator to audibly input a tone sequence and for the electronic learning aid to attempt to mimic the sequence of tones.

Electronic handheld translator having miniature electronic speech synthesis chip

An electronic handheld talking translator including a speech synthesis integrated circuit device. The speech synthesis integrated circuit device includes a digital filter, a voiced/unvoiced excitation circuit, a speech parameter interpolator, an input parameter decoder, a digital-to-analog converter, a speaker and associated timing circuits. A non-volatile memory stores digital data representative of the correct spellings of selected words in a foreign language and the model vocal tract control data necessary to control the speech synthesis circuit in a manner to cause the selected words to be audibly pronounced by the translator.

Design case history: Speak & Spell learns to talk

Describes how a hand-held, low-cost electronic spelling aid with a speech output was designed. A major problem was the synthesis of speech of a quality acceptable to the consumer.

Variable frame length data converter for a speech synthesis circuit

A speech synthesis circuit is provided with a variable frame length data converter and the speech synthesizer is preferably integrated on an integrated circuit chips. The variable frame length data converter reduces the amount of data required to synthesizer human speech at a given quality level. Preferably, a full frame of data includes, a pitch parameter, an energy parameter, a repeat bit and a plurality of speech coefficients. Each parameter or coefficient has a preselected length, but each frame has a variable number of parameters or coefficients associated therewith. The parameters and coefficients are encoded and a particular code of the pitch parameter indicates that the speech is to be unvoiced. An unvoiced frame includes fewer coefficients that a voiced frame and the converter detects this particular pitch parameter and automatically sets the unsent coefficients to zero. The converter also detects the state of the repeat bit for controlling the synthesizing to use the coefficients received during the previous frame as the coefficient to be used to generate speech in response to the present frame. In this embodiment, when the repeat bit comes up, new pitch and energy parameters are inputted therewith. Further, the converters preferably detects particular codes in the energy parameter for determining when a pause occurs or when the last frame of data has been sent.

Integrated speech synthesis circuit with internal and external excitation capabilities

A speech synthesis circuit implementable in an integrated circuit device, capable of converting frames of data into analog signals representative of human speech. The frames of data are comprised of digital representations of values of pitch, energy and certain filter coefficients, which are stored in non-volatile memory. The filter coefficients are utilized to control a linear predictive filter which is excited by voiced and unvoiced excitations stored in non-volatile memory. A control circuit coupling the excitation signals to the linear predictive filter allows the operator to select an external excitation signal rather than precalculated stored excitation signals. Thus, the synthesizer may be utilized in a vocoder application, wherein a residual excitation signal transmitted from an analysis circuit may be utilized as the excitation signal.

Method and apparatus for speech synthesis filter excitation

A speech synthesis system utilizing a linear predictive filter. Voiced and unvoiced excitations are applied to the filter to produce a digital signal representative of human speech. The voiced excitation is provided by a repeating chirp function stored in memory. The unvoiced excitation consists of two excitation signals of opposite sign, stored in programmable memory and randomly addressed. The programmable storage of unvoiced excitation signals allows gain scaling between voiced and unvoiced excitation to be easily accomplished.

Quality comparison measure for linear predictive systems

This paper reports the results of an investigation of a computable Quality Comparison Measure (called the QCM) for linear predictive systems. The measure described is easily obtained by a synthesis-analysis procedure. It is a weighted combination of differences between the input and output speech parameters for a series of spoken sentences. Results are presented that demonstrate a high correlation between QCM and listener preference scores. The QCM offers an alternative to costly and time consuming formal listening procedures.

Piecewise linear predictive coding (PLPC)

A great deal of current research in the area of narrowband digital speech compression makes use of the Linear Prediction Coding (LPC) algorithm to extract the vocal track spectrum. This paper describes a technique that splits the spectrum into two equal halves and performs a piecewise LPC approximation to each half. By taking advantage of the classical benefits of piecewise approximation, the fidelity is expected to be higher than standard LPC. In addition, by making use of under-sampling and spectrum folding, computational requirements are reduced by about 40%. PLPC has been implemented in real time on the CSP-30 computer at the Speech Research and Development Facility of the Communications Security Engineering Office (DCW) at ESD.