George Lentaris

SPARTAN: Developing a Vision System for Future Autonomous Space Exploration Robots

Mars exploration is expected to remain a focus of the scientific community in the years to come. A Mars rover should be highly autonomous because communication between the rover and the terrestrial operation center is difficult, and because the vehicle should spend as much of its traverse time as possible moving. Autonomous behavior of the rover implies that the vision system provides both a wide view to enable navigation and three-dimensional (3D) reconstruction, and at the same time a close-up view ensuring safety and providing reliable odometry data. The European Space Agency funded project “SPAring Robotics Technologies for Autonomous Navigation” (SPARTAN) aimed to develop an efficient vision system to cover all such aspects of autonomous exploratory rovers. This paper presents the development of such a system, starting from the requirements up to the testing of the working prototype. The vision system was designed with the intention of being efficient, low-cost, and accurate and to be implemented using custom-designed vectorial processing by means of field programmable gate arrays (FPGAs). A prototype of the complete vision system was developed, mounted on a basic mobile robot platform, and tested. The results on both real-world Mars-like and long-range simulated data are presented in terms of 3D reconstruction and visual odometry accuracy, as well as execution speed. The developed system is found to fulfill the set requirements.

HW/SW Codesign and FPGA Acceleration of Visual Odometry Algorithms for Rover Navigation on Mars

Future Mars exploration missions rely heavily on high-mobility autonomous rovers equipped with sophisticated scientific instruments and possessing advanced navigational capabilities. Increasing their navigation velocity and localization accuracy is essential for enabling these rovers to explore large areas on Mars. Contemporary Mars rovers move slowly, partially due to the long execution time of complex computer vision algorithms running on their slow space-grade CPUs. This paper exploits the advent of high-performance space-grade field-programmable gate arrays (FPGAs) to accelerate the navigation of future rovers. Specifically, it focuses on visual odometry (VO) and performs HW/SW codesign to achieve one order of magnitude faster execution and improved accuracy. Conforming to the specifications of the European Space Agency, we build a proof-of-concept system on an HW/SW platform with processing power resembling that to be available onboard future rovers. We develop a codesign methodology adapted to the rovers specifications, design parallel architectures, and customize several feature extraction, matching, and motion estimation algorithms. We implement and evaluate five distinct HW/SW pipelines on a Virtex6 FPGA and a 150 MIPS CPU. We provide a detailed analysis of their cost-time-accuracy tradeoffs and quantify the benefits of employing FPGAs for implementing VO. Our solution achieves a speedup factor of 16× over a CPU-only implementation, handling a stereo image pair in less than 1 s, with a 1.25% mean positional error after a 100 m traverse and an FPGA cost of 54 K LUTs and 1.46-MB RAM.

Reduced Complexity Superresolution for Low-Bitrate Video Compression

Evolving video applications impose requirements for high image quality, low bitrate, and/or small computational cost. This paper combines state-of-the-art coding and superresolution (SR) techniques to improve video compression both in terms of coding efficiency and complexity. The proposed approach improves a generic decimation-quantization compression scheme by introducing low complexity single-image SR techniques for rescaling the data at the decoder side and by jointly exploring/optimizing the downsampling/upsampling processes. The enhanced scheme achieves improvement of the quality and systems complexity compared with conventional codecs and can be easily modified to meet various diverse requirements, such as effectively supporting any off-the-shelf video codec, for instance H.264/Advanced Video Coding or High Efficiency Video Coding. Our approach builds on studying the generic schemes parameterization with common rescaling techniques to achieve 2.4-dB peak signal-to-noise ratio (PSNR) quality improvement at low-bitrates compared with the conventional codecs and proposes a novel SR algorithm to advance the critical bitrate at the level of 10 Mb/s. The evaluation of the SR algorithm includes the comparison of its performance to other image rescaling solutions of the literature. The results show quality improvement by 5-dB PSNR over straightforward interpolation techniques and computational time reduction by three orders of magnitude when compared with the highly involved methods of the field. Therefore, our algorithm proves to be most suitable for use in reduced complexity downsampled compression schemes.

SPARTAN project: On profiling computer vision algorithms for rover navigation

The exploration of Mars is one of the main goals for NASA/ESA, as confirmed by past and recent activities. One of the most challenging tasks for these missions is the autonomous robots navigation. Existing approaches incorporate vision-based solutions and exhibit remarkable results in term of accuracy. Unfortunately, these approaches affect mostly computational and memory intensive algorithms running on software-level. In this paper, we introduce a novel methodology for efficient implementation of computer vision algorithms for the SPARTAN project (ExoMars 2018 mission). Experimental results prove the effectiveness of the introduced solution, as compared to a software-based implementation.

Study of interpolation filters for motion estimation with application in H.264/AVC encoders

The current paper studies low-complexity image super-resolution techniques for improving the motion estimation process of video encoding. Aiming at speeding up the generation of candidate blocks during the computationally intensive search algorithm, we present interpolation techniques with reduced cost compared to standard 6-tap filtering procedures. Furthermore, we compare their performance to that of commonly used half-pixel interpolation techniques with respect to the resulting image quality and the processing time. The research has been based on using a typical fractional motion estimation algorithm preceding the processing of the H.264/AVC standard motion compensation, and thus, the research benefits the design of H.264/AVC encoders.

An Efficient H.264 VLSI Advanced Video Encoder

Video technology evolution has boosted the need for the H.264/AVC encoder with real-time performance. In order to meet such need the present paper presents a VLSI H.264/AVC encoder architecture and the relevant details on design and implementation of the specific modules. The encoder design complies with the reference software encoder of the standard and follows the baseline profile level 3.0. The encoder constitutes an IP-core and/or stand-alone solution targeting to low area applications. The architecture achieves maximum throughput of 30 frames/sec with frame size 1024times768. Results and performance measurements of the entire encoder have been validated on FPGA and VLSI .18 mum.

Acceleration techniques and evaluation on multi-core CPU, GPU and FPGA for image processing and super-resolution

Super-resolution (SR) techniques constitute a key element in image applications, which need high-resolution reconstruction, while in the worst case, only a single low-resolution observation is available. SR techniques involve computationally demanding processes, and thus, researchers are currently focusing on SR performance acceleration. Aiming at improving the SR performance, the current paper builds up on the characteristics of the L-SEABI SR method to introduce parallelization techniques for GPUs and FPGAs. The proposed techniques accelerate GPU reconstruction of ultra-high definition content, by achieving three (3

Configurable baseband digital transceiver for Gbps wireless 60 GHz communications

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