Konstantinos Maragos

Application performance improvement by exploiting process variability on FPGA devices

Process variability is known to be increasing with technology scaling in IC fabrication, thereby degrading the overall performance of the manufactured devices. The current paper focuses on the variability effect in FPGAs and the possibility to boost the performance of each device at run-time, after fabrication, based on the individual characteristics of this device. First, we develop a sensing infrastructure involving a wide network of customized ring oscillators to measure intra-chip and inter-chip variability in 28nm FPGAs, i.e., in eight Xilinx Zynq XC7Z020T-1CSG324 devices. Second, we develop a closed-loop framework based on dynamic reconfiguration of clock tiles, I/O data sniffing, HW/SW communication, and verification with test vectors, to dynamically increase the operating frequency in Zynq while preserving its correctness. Our results show intra-chip variability in the area of 5.2% to 7.7% and inter-chip variability up to 17%. Our framework improves the performance of example FIR designs by up to 90.3% compared to the SW tool reports and shows speed difference among devices by up to 12.4%.

High-Performance Embedded Computing in Space: Evaluation of Platforms for Vision-Based Navigation

Vision-based navigation has become increasingly important in a variety of space applications for enhancing autonomy and dependability. Future missions, such as active debris removal for remediating...

SPARTAN/SEXTANT/COMPASS: Advancing Space Rover Vision via Reconfigurable Platforms

Targeting enhanced navigational speed and autonomy for the space exploration rovers, researchers are gradually turning to reconfigurable computing and FPGAs. High-density space-grade FPGAs will enable the acceleration of high-complexity computer vision algorithms for improving the localization and mapping functions of the future Mars rovers. In the projects SPARTAN/SEXTANT/COMPASS of the European Space Agency, we study the potential use of FPGAs for implementing a variety of stereo correspondence, feature extraction, and visual odometry algorithms, all with distinct cost-performance tradeoffs. The most efficient of the developed accelerators will assist the slow space-grade CPU in completing the visual tasks of the rover faster, by one order of magnitude, and thus, will allow the future missions to visit larger areas on Mars. Our work bases on a custom HW/SW co-design methodology, parallel architecture design, optimization techniques, tradeoff analysis, and system tuning with Martian-like scenarios.

An Evolutionary Algorithm for Netlist Partitioning Targeting 3-D FPGAs

Three-dimensional (3-D) chip stacking is considered as the silver bullet technology to preserve Moores momentum and fuel the next wave of consumer electronics. However, the benefits of such an integration technology have not yet been explored due to limitations posed mostly by the lack of efficient tools to support application mapping onto these devices. This letter introduces a framework based on a genetic algorithm for netlist partitioning targeting 3-D reconfigurable platforms. Experimental results prove the efficiency of our solution, as we achieve average reduction of the number of utilized through-silicon vias (TSVs) up to 17% for comparable performance metrics against relevant state-of-the-art algorithms.

A Framework Exploiting Process Variability to Improve Energy Efficiency in FPGA Applications

As technology node scales-down and process variability increases, the vendors impose even more conservative guard-bands to prevent potential malfunction of their microchips. However, this approach introduces considerable amounts of unexploited performance to individual chips, which can be harvested by developing novel customization tools. In the current work, we focus on the exploitation of process variability in modern FPGA chips to provide more energy efficient solutions. We propose a framework that i) generates variability maps characterizing the energy efficiency of commercial chips and ii) combines voltage and frequency scaling to limit the power dissipation of any given design for a given set of performance constraints. Experimental results on Zynq XC7Z020 28nm FPGAs show that the developed framework achieves up to 28.3% power reduction while maintaining the performance and functional integrity of realistic benchmarks. Moreover, by selecting the most efficient chip, we achieve up to 5.1% additional power savings.

A Flexible, High-Performance FPGA Implementation of a Feed-Forward Equalizer for Optical Interconnects up to 112 Gb/s

Commodity optoelectronic components and multi-level modulation formats are combined nowadays in optical networks to increase their throughput while decreasing their cost. To overcome the inherent limitations of such interconnects, research focuses on digital equalizers that compensate for the effects of the developed channels. The current paper proposes the use of FPGAs to enhance the speed, power and flexibility of digital equalization for the next generation 100 Gb/s rack-to-rack optical links in datacenters. We present the high-performance hardware architecture of a flexible feed-forward equalizer (FFE) with multiple reconfigurations. We describe parallelization techniques to accelerate FFE, accuracy analysis for various FFE scenarios, as well as a design space exploration leading to a fine-tuned and platform-dependent FFE customization. Our final implementation on a single Xilinx XC7VH580T FPGA device with GTZ transceivers can support a single link of up to 112 Gbps (56 GSa/s with PAM-4 modulation) and 2.26⋅10−6 Bit-Error-Rate.

FPGA acceleration of hyperspectral image processing for high-speed detection applications

Recent advances in photonics and imaging technology allow the development of cutting-edge, lightweight hyperspectral sensors, both push-broom/line-scanning and snapshot/frame. At the same time, emerging applications in robotics, food inspection, medicine and earth observation are posing critical challenges on real-time processing and computational efficiency, both in terms of accuracy and power consumption. In this direction, in the current paper, we accelerate hyperspectral processing kernels by utilizing FPGAs, i.e., Zynq-7000 SoC, to perform similarity-based matching of spectral signatures. We propose a custom HW architecture based on multi-level parallelization, modularity, and parametric VHDL coding, which allows for in-depth design space exploration and trade-off analysis. Depending on configuration, our implementation processes 22–107 Megapixels per second providing an acceleration of 40–355x vs Intel-i3 CPU and 360-104x vs the embedded ARM Cortex A9, whereas the overall detection quality ranges from 56% to 97% when evaluated with multiple objects and images of 285 spectral channels.

Project HIPNOS: Case Study of High Performance Avionics for Active Debris Removal in Space

The Clean Space initiative of the European Space Agency (ESA) seeks to decrease the environmental impact of space programmes by focusing, among others, on Active Debris Removal (ADR) and eDeorbit. In this direction, one of the main challenges is to autonomously track and approach a big non-cooperative satellite such as ENVISAT. To achieve the high level of autonomy required in this phase of the ADR mission, vision based navigation will guide a chaser spacecraft in real-time based on high-definition images acquired and processed on-board at high frame-rates. The increased complexity of these computer vision algorithms mandates the development and use of high performance avionics to provide one order of magnitude faster execution than todays conventional space-grade processors. In the context of ESAs project HIPNOS (HIgh Performance avionics solutioN for advanced and complex GNC Systems), we study algorithms and avionics architectures suitable for ADR. The examined algorithms base on image feature extraction and the architectures base on COTS SoC-FPGA devices. Preliminary analysis highlights the benefits of employing this avionics solution in future space missions.

On supporting rapid prototyping of embedded systems with reconfigurable architectures

Abstract Reducing time-to-market while improving product quality is a big challenge. This paper proposes a software-supported framework for rapid prototyping that offers a concurrent fast hardware/software system-level design. The introduced framework enables the constant evaluation and verification of the prototype under development, while it provides automatic functionality mapping to hardware via High-Level Synthesis techniques. We evaluate our framework and its software instantiation with a computer vision algorithm. Based on our experimentation, we show that our approach reduces the development time by almost 64×, it prunes the hardware design space by 34×, while maintaining designs that trade-off high Quality-of-Report on the Pareto frontier.

A Co-Design Approach For Rapid Prototyping Of Image Processing On SoC FPGAs

Achieving real-time performance in image processing with embedded devices poses a very challenging task due to the computationally and memory intensive nature of the algorithms. The FPGA platforms provide very attractive solutions in such applications, because they support highly parallel processing with low power consumption. In this paper we present an approach to increase productivity when developing real-time image processing algorithms on SoC FPGA devices. Our approach is centered around the fast communication of the HW and SW components and the use of an open-source operating system hosted on the existing embedded processor. Based on this approach we decrease time-to-market while at the same time we avoid hindering the real-time operation of the system. To demonstrate the capabilities of the proposed system, as a proof of concept, we use the well known Harris detection algorithm and the Xilinx Zynq XC7Z020 FPGA device. We present an in-depth performance analysis regarding the resource utilization of the FPGA, the operation frequency, the communication overhead and the power consumption.