Georgios N. Selimis

Evaluation of 90nm 6T-SRAM as Physical Unclonable Function for secure key generation in wireless sensor nodes

Due to the unattended nature of WSN (Wireless Sensor Network) deployment, each sensor can be subject to physical capture, cloning and unauthorized device alteration. In this paper, we use the embedded SRAM, often available on a wireless sensor node, for secure data (cryptographic keys, IDs) generation which is more resistant to physical attacks. We evaluate the physical phenomenon that the initial state of a 6T-SRAM cell is highly dependent on the process variations, which enables us to use the standard SRAM circuit, as a Physical Unclonable Function (PUF). Important requirements to serve as a PUF are that the start-up values of an SRAM circuit are uniquely determined, unpredictable and similar each time the circuit is turned on. We present the evaluation results of the internal SRAM memories of low power ICs as PUFs and the statistical analysis of the results. The experimental results prove that the low power 90nm commercial 6T-SRAMs are very useful as a PUF. As far as we know, this is the first work that provides an extensive evaluation of 6T-SRAM-based PUF, at different environmental, electrical, and ageing conditions to representing the typical operating conditions of a WSN.

A Lightweight Security Scheme for Wireless Body Area Networks: Design, Energy Evaluation and Proposed Microprocessor Design

In order for wireless body area networks to meet widespread adoption, a number of security implications must be explored to promote and maintain fundamental medical ethical principles and social expectations. As a result, integration of security functionality to sensor nodes is required. Integrating security functionality to a wireless sensor node increases the size of the stored software program in program memory, the required time that the sensor’s microprocessor needs to process the data and the wireless network traffic which is exchanged among sensors. This security overhead has dominant impact on the energy dissipation which is strongly related to the lifetime of the sensor, a critical aspect in wireless sensor network (WSN) technology. Strict definition of the security functionality, complete hardware model (microprocessor and radio), WBAN topology and the structure of the medium access control (MAC) frame are required for an accurate estimation of the energy that security introduces into the WBAN. In this work, we define a lightweight security scheme for WBAN, we estimate the additional energy consumption that the security scheme introduces to WBAN based on commercial available off-the-shelf hardware components (microprocessor and radio), the network topology and the MAC frame. Furthermore, we propose a new microcontroller design in order to reduce the energy consumption of the system. Experimental results and comparisons with other works are given.

13.2 A 3.7mW-RX 4.4mW-TX fully integrated Bluetooth Low-Energy/IEEE802.15.4/proprietary SoC with an ADPLL-based fast frequency offset compensation in 40nm CMOS

This paper presents an ultra-low-power (ULP) fully-integrated Bluetooth Low-Energy(BLE)/IEEE802.15.4/proprietary RF SoC for Internet-of-Things applications. Ubiquitous wireless sensors connected through cellular devices are becoming widely used in everyday life. A ULP RF transceiver is one of the most critical components that enables these emerging applications, as it can consume up to 90% of total battery energy. Furthermore, a low-cost radio design with an area-efficient fully integrated RF SoC is an important catalyst for developing such applications. By employing a low-voltage digital-intensive architecture, the presented SoC is fully compliant with BLE and IEEE802.15.4 PHY/Data-link requirements and achieves state-of-the-art power consumption of 3.7mW for RX and 4.4mW for TX.

Software and Hardware Issues in Smart Card Technology

An efficient and strongly secure smart card mechanism involves the use of a technological background taken from the fields of computers, VLSI design and material science. The result of such a mixture is a miniature, fully operational, computation system. The nature of the data involved in smart card transactions and smart card intended uses, introduce another important factor in the smart card design mechanism which is security. The evolution of VLSI technology allows the efficient implementation of costly cryptographic operations in the smart card design methodology. Apart from the traditional cryptographic algorithms, additional techniques and special design materials have been introduced in order to protect the smart card system from cryptanalytic attacks. New architectures of software design, like object-oriented programming, give the opportunity to implement programmable multi-application cards. Thus, smart cards are transformed into highly secure devices and their establishment in the modern computer market can be considered certain. This establishment is bound to finance upcoming research in smart cards so that this product can become the basic component of electronic commerce worldwide.

Exploration of cryptographic ASIP designs for wireless sensor nodes

We present the design of 4 Application Specific Instruction Set Processors (8-bit, 32-bit, 64-bit and 128-bit ASIP) which provide typical 16-bit general instructions and accelerate a common cryptographic domain. The ASIPs support the following security services: data confidentiality, data authentication, data integrity and replay attack protection and their design is appropriate for wireless sensor networks. The corresponding software for each ASIP has been optimized in terms of clock cycles and memory accesses. We evaluate the 4 ASIPs in terms of performance, power consumption, energy dissipation and area occupation. When our most energy efficient design (128-bit ASIP) operates on AES-CCM-32 security mode at a clock frequency of 100 MHz, it dissipates 41.86 nJ achieving a maximum throughput of 21.76 Mbps, while at a lower clock frequency of 4.61 MHz, it achieves a throughput of 1 Mbps, a typical value in the WSN, and dissipates energy of 35.20 nJ. The corresponding area overhead, for 90nm technology, excluding the memories, is 34.3K NAND2 equivalents. Comparisons with other works are given.

Bulk encryption crypto-processor for smart cards: design and implementation

The evolution of a cipher has no practical impact if it has only a theoretical background. Every encryption algorithm should exploit as much as possible the conditions of the specific system without omitting the physical, area and timing limitations. The smart card environment lacks system resources, but commercial and economic transactions via smart cards demand the use of certificated and secure cryptographic methods. This fact requires new ways of designing architectures for secure and reliable smart card systems. A crypto-processor architecture and its VLSI implementation for smart card bulk encryption is proposed. The proposed architecture achieves 30% area resource reduction and has a throughput value much greater than smart card standards specify.

Low power cryptography

Today more and more sensitive data is stored digitally. Bank accounts, medical records and personal emails are some categories that data must keep secure. The science of cryptography tries to encounter the lack of security. Data confidentiality, authentication, non-reputation and data integrity are some of the main parts of cryptography. The evolution of cryptography drove in very complex cryptographic models which they could not be implemented before some years. The use of systems with increasing complexity, which usually are more secure, has as result low throughput rate and more energy consumption. However the evolution of cipher has no practical impact, if it has only theoretical background. Every encryption algorithm should exploit as much as possible the conditions of the specific system without omitting the physical, area and timing limitations. This fact requires new ways in design architectures for secure and reliable crypto systems. A main issue in the design of crypto systems is the reduction of power consumption, especially for portable systems as smart cards.

Crypto processor for contactless smart cards

In this paper a crypto processor for contactless smart cards is presented. The proposed architecture is based on DES algorithm standard. The introduction in the proposed system a power management unit results in a significant power consumption reduction. The use of feedback design techniques reduces the required silicon area. The overall system throughput satisfies the contactless smart card data rate demands. The proposed system operates in 55 MHz frequency with maximum data rate 42.5 Mbps. A 50% power reduction, in comparison with conventional implementations, has estimated mainly due to the switching activity and the total memory accesses reduction. Additional techniques for silicon area reduction are also presented.

Sub-meter UWB localization: Low complexity design and evaluation in a real localization system

Accurate indoor localization is a key component for many applications such as tracking, indoor navigation, home/industrial automation, gaming and intelligent transportation systems. Impulse radio ultrawide-band (IR-UWB) allows sub-meter accurate localization due to its inherent high time resolution. The accuracy of localization depends on the detection moment of the direct path signal (Time Of Arrival: TOA). Many studies focus only on TOA estimation without providing a close to system approach. Unlike these studies, we provide a system compatible solution which takes into account low resources design constraints. In this paper, a) we propose a design for sub-meter localization using 802.15.4a UWB compliant signals, b) we integrate our design in a real localization system and c)we evaluate its accuracy in a real scenario. The proposed design is robust to multipath environment by being on the fly adjustable to the existing channel properties. It accomplishes high accuracy and it is ideal for limited resource systems, meeting the low resources requirements of IEEE 802.15.4a standard. The measured error is around 5-10 cm in a multipath environment for 1 GHz sampling rate. This work is novel and it tries to bridge the gap between theoritical digital signal processing solutions presented in literature and the feasibility of a low cost implementation for sensor nodes.

Cipher block based authentication module: A hardware design perspective

Message Authentication Codes (MACs) are widely used in order to authenticate data packets, which are transmitted thought networks. Typically MACs are implemented using modules like hash functions and in conjunction with encryption algorithms (like Block Ciphers), which are used to encrypt the transmitted data. However NIST in May 2005 issued a standard, addressing certain applications and their needs, defining a way to implement MACs through FIPS-approved and secure block cipher algorithms. In this paper the best performing implementation of the CMAC standard is presented, in terms of throughput, along with an efficient AES design and implementation.