Gerardo Gutierrez-Heredia

Chronic softening spinal cord stimulation arrays

OBJECTIVE We sought to develop a cervical spinal cord stimulator for the rat that is durable, stable, and does not perturb the underlying spinal cord. APPROACH We created a softening spinal cord stimulation (SCS) array made from shape memory polymer (SMP)-based flexible electronics. We developed a new photolithographic process to pattern high surface area titanium nitride (TiN) electrodes onto gold (Au) interconnects. The thiol-ene acrylate polymers are stiff at room temperature and soften following implantation into the body. Durability was measured by the duration the devices produced effective stimulation and by accelerated aging in vitro. Stability was measured by the threshold to provoke an electromyogram (EMG) muscle response and by measuring impedance using electrochemical impedance spectroscopy (EIS). In addition, spinal cord modulation of motor cortex potentials was measured. The spinal column and implanted arrays were imaged with MRI ex vivo, and histology for astrogliosis and immune reaction was performed. MAIN RESULTS For durability, the design of the arrays was modified over three generations to create an array that demonstrated activity up to 29 weeks. SCS arrays showed no significant degradation over a simulated 29 week period of accelerated aging. For stability, the threshold for provoking an EMG rose in the first few weeks and then remained stable out to 16 weeks; the impedance showed a similar rise early with stability thereafter. Spinal cord stimulation strongly enhanced motor cortex potentials throughout. Upon explantation, device performance returned to pre-implant levels, indicating that biotic rather than abiotic processes were the cause of changing metrics. MRI and histology showed that softening SCS produced less tissue deformation than Parylene-C arrays. There was no significant astrogliosis or immune reaction to either type of array. SIGNIFICANCE Softening SCS arrays meet the needs for research-grade devices in rats and could be developed into human devices in the future.

Solution-deposited Al2O3 dielectric towards fully-patterned thin film transistors on shape memory polymer

Solution deposition has potential for highly cost-effective fabrication of thin film transistors (TFTs) on flexible substrates. Shape memory polymer (SMP), with improved thermal mechanical response, may enable large-area flexible devices, as well as add control to the product shape and modulus. Until date, TFTs made on SMP substrates have been limited to vacuum-deposition methods. While TFTs processed through more economical solution-based techniques achieve device performance close to their vacuum-processed counterparts, they have not yet been demonstrated on SMP substrates due to the required high calcination temperatures (> 500 °C). To take full advantages of SMP, low temperature (< 200 °C) solution-based processing is highly desirable. Compatibility of the deposition process with the substrate and previously deposited films is essential. Here, we develop a process that incorporates direct UV patterning that would allow for fabrication of oxide TFTs on SMP using a reduced number of processing steps. Rigid In2O3 TFTs, deposited from solution-combustion synthesis, are fabricated on Si substrates with different solution-deposited dielectrics to evaluate their potential for transferring to SMP.

Solution-Based CdS on HfO 2 Thin Films for High-Gain and Low-Voltage Unipolar Inverters

We demonstrate low-temperature processed and high-gain unipolar inverters operating at voltages as low as VD = 1 V. A maximum gain for a two-transistor unipolar inverter of 153 was achieved at VD = 5 V with the advantage of using a solution-based n-type semiconductor and an entire fabrication process below 150 °C. We evaluate the impact of the gate dielectric thickness on the main thin-film transistor (TFT) parameters and operation voltage. In addition, we compare the conventional MOSFET square-law model indistinctly used in TFTs with a model specifically developed for TFTs. We demonstrate a methodology to model the TFT electrical characteristics and use the extracted parameters in SPICE simulations to evaluate different inverter configurations. Finally, we validate the SPICE simulations with our experiential results.