Gerhard Koops

Split-gate Resurf Stepped Oxide (RSO) MOSFETs for 25V applications with record low gate-to-drain charge

This paper presents a split-gate version of the resurf stepped oxide (RSO) MOSFET. Splitting the gate enables a drastic reduction of the gate-to-drain capacitance intrinsic to the RSO device concept while keeping all the benefits of the RESURF effect. We achieved a record on- resistance of 3.8 mOmegamm2 and gate-to-drain charge of 0.9 nC.mm-2 at a breakdown voltage of 35 V for a pitch of 1.3 mum (0.8 mum trench width). The switching losses of our split-gate RSO MOSFET are 4 times better than the best published data in the same voltage range.

A piezo-resistive resonant MEMS amplifier

A MEMS resonator using electrostatic to piezo-resistive transduction is demonstrated to be capable of simultaneous signal filtering and amplification. The mechanical resonance serves as a high Q electrical filter, while the piezo-resistive readout allows for signal amplification. Amplification factors up to 4.6 dB and Q values up to 60,000 are obtained for a 15 MHz resonator.

56 MHZ piezoresistive micromechanical oscillator

A fully functional oscillator has been developed, based on a resonator with an electrostatic-to-piezoresistive transduction. Both resonator and amplifier IC have been processed on a SOI wafer with identical SOI layer thickness of 1.5 μm. The resonator is a bulk-acoustic ‘dogbone’ design, for which an extended electrical model is presented. At an oscillation frequency of 56.1 MHz the oscillator consumes 6.1 mW and reaches a phase noise of −102 dBc/Hz at 1 kHz offset from carrier.

Design optimization of field-plate assisted RESURF devices

A mathematical model for optimizing the 2-D potential distribution in the drift region of field-plate (FP)-assisted RESURF devices (Fig. 1) is presented. The proposed model extends earlier work [1-2] by including top-bottom dielectric asymmetry (typical in SOI devices [3]), non-zero field plate potentials VFP and grading of design parameters other than drift region doping. This generally-applicable, TCAD-verified [4], model provides a guideline for optimizing the drain extension in a wide range of FP-assisted RESURF devices.

Spontaneous mechanical oscillation of a DC driven single crystal

A micrometre-scale device that exploits the piezoresistive characteristics of silicon acts like an engine, converting heat into mechanical work in one mode of operation, and, in another, like a refrigerator, suppressing mechanical fluctuations.There is a large interest to decrease the size of mechanical oscillators since this can lead to miniaturization of timing and frequency referencing devices, but also because of the potential of small mechanical oscillators as extremely sensitive sensors. Here we show that a single crystal silicon resonator structure spontaneously starts to oscillate when driven by a constant direct current (DC). The mechanical oscillation is sustained by an electrothermomechanical feedback effect in a nanobeam, which operates as a mechanical displacement amplifier. The displacement of the resonator mass is amplified, because it modulates the resistive heating power in the nanobeam via the piezoresistive effect, which results in a temperature variation that causes a thermal expansion feedback-force from the nanobeam on the resonator mass. This self-amplification effect can occur in almost any conducting material, but is particularly effective when the current density and mechanical stress are concentrated in beams of nano-scale dimensions.

Piezoresistive ring-shaped MEMS resonator

We have previously reported a new class of MEMS resonators based on the piezoresistive readout principle and extensional vibration mode. Those devices suffer from unwanted mode-coupling at large vibration amplitudes, giving rise to problems such as beat patterns in the time signal. In this paper, we present a novel type of piezoresistive resonator that has a shape of a ring and operates in a flexural in-plane mode shape. The new resonators can be operated at larger excitation forces without having the mode-coupling problem, as compared to the conventional piezoresistive resonators.

Comparison of electrical techniques for temperature evaluation in power MOS transistors

Three electrical techniques (pulsed-gate, AC-conductance and sense-diode) for temperature evaluation in power MOS transistors have been experimentally compared on the same device. The device under test is a silicon-on-insulator (SOI) laterally-diffused MOSFET (LDMOS) design with embedded sense-diodes in the center and at the edge of the device for providing local temperature information. On-wafer measurements have been performed on a thermal chuck in the temperature range 25-200°C to extract self-heating information and predict the junction temperature for different biasing conditions. Good agreement (within 10%) between the different techniques is achieved, evidencing that reliable temperature estimations can be made using each of the proposed electrical techniques. As a result, factors other than experimental accuracy will play a role in the choice of the most adequate technique for the application of interest. Guidelines for this choice are provided in a benchmarking analysis accounting for ease of application, temperature calibration and accuracy of the results.

Integrated heat sinks for SOI power devices

Silicon on insulator (SOI) technology for power devices offers many distinct advantages compared to bulk Si technology, however in high power applications the buried oxide (BOX) layer can impede heat transport towards the backside of the silicon substrate. This paper demonstrates integration of heat sinks in SOI power devices to improve thermal performance. The heat sinks are formed by polysilicon plugs through the BOX layer that significantly reduce thermal resistance and thus increase the safe operating limits of the technology. The effectiveness of the integrated heat sinks was evaluated by the experimental AC conductance method and by thermal finite element modeling. The integrated heat sinks are shown to reduce the thermal resistance by 15%, improving both thermal and electrical performance of the SOI transistors.

ISPSD '07 Charitat Award; Split-Gate Resurf Stepped Oxide (RSO) MOSFETS for 25V Applications with Record Low Gate-to-Drain Charge

This paper presents a split-gate version of the Resurf Stepped Oxide (RSO) MOSFET. Splitting the gate enables a drastic reduction of the gate-to-drain capacitance intrinsic to the RSO device concept while keeping all the benefits of the RESURF effect. We achieved a record on-resistance of 3.8 m¿mm2 and gate-to-drain charge of 0.9 nCmm2 at a breakdown voltage of 35V for a pitch of 1.3 mm (0.8 mm trench width). The switching losses of our split-gate RSO MOSFET are 4 times better than the best published data in the same voltage range.