Gerhard Schrom

A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS

Current developments in microprocessor design favor increased core counts over frequency scaling to improve processor performance and energy efficiency. Coupling this architectural trend with a message-passing protocol helps realize a data-center-on-a-die. The prototype chip (Figs. 5.7.1 and 5.7.7) described in this paper integrates 48 Pentium™ class IA-32 cores [1] on a 6×4 2D-mesh network of tiled core clusters with high-speed I/Os on the periphery. The chip contains 1.3B transistors. Each core has a private 256KB L2 cache (12MB total on-die) and is optimized to support a message-passing-programming model whereby cores communicate through shared memory. A 16KB message-passing buffer (MPB) is present in every tile, giving a total of 384KB on-die shared memory, for increased performance. Power is kept at a minimum by transmitting dynamic, fine-grained voltage-change commands over the network to an on-die voltage-regulator controller (VRC). Further power savings are achieved through active frequency scaling at the tile granularity. Memory accesses are distributed over four on-die DDR3 controllers for an aggregate peak memory bandwidth of 21GB/s at 4× burst. Additionally, an 8-byte bidirectional system interface (SIF) provides 6.4GB/s of I/O bandwidth. The die area is 567mm2 and is implemented in 45nm high-к metal-gate CMOS [2].

A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package

We demonstrate an integrated buck dc-dc converter for multi-V/sub CC/ microprocessors. At nominal conditions, the converter produces a 0.9-V output from a 1.2-V input. The circuit was implemented in a 90-nm CMOS technology. By operating at high switching frequency of 100 to 317 MHz with four-phase topology and fast hysteretic control, we reduced inductor and capacitor sizes by three orders of magnitude compared to previously published dc-dc converters. This eliminated the need for the inductor magnetic core and enabled integration of the output decoupling capacitor on-chip. The converter achieves 80%-87% efficiency and 10% peak-to-peak output noise for a 0.3-A output current and 2.5-nF decoupling capacitance. A forward body bias of 500 mV applied to PMOS transistors in the bridge improves efficiency by 0.5%-1%.

Review of On-Chip Inductor Structures With Magnetic Films

A comparison of on-chip inductors with magnetic materials from previous studies is presented and examined. Results from on-chip inductors with magnetic material integrated into a 90 nm CMOS processes are presented. The inductors use copper metallization and amorphous Co-Zr-Ta magnetic material. Inductance densities of up to 1700 nH/mm2 were obtained thanks to inductance increases of up to 31 times, significantly greater than previously published on-chip inductors. With such improvements, the effects of eddy currents, skin effect, and proximity effect become clearly visible at higher frequencies. Co-Zr-Ta was chosen for its good combination of high permeability, good stability at high temperature (> 250degC), high saturation magnetization, low magnetostriction, high resistivity, minimal hysteretic loss, and compatibility with silicon technology. The Co-Zr-Ta alloy can operate at frequencies up to 9.8 GHz, but trade-offs exist between frequency, inductance, and quality factor. Our inductors with thick copper and thicker magnetic films have dc resistances as low as 0.04 Omega, and quality factors of up to 8 at frequencies as low as 40 MHz.

FIVR — Fully integrated voltage regulators on 4th generation Intel® Core™ SoCs

Intels® 4th generation Core™ microprocessors are powered by Fully Integrated Voltage Regulators (FIVR). These 140 MHz multi-phase buck regulators are integrated into the 22nm processor die, and feature up to 80 MHz unity gain bandwidth, non-magnetic package trace inductors and on-die MIM capacitors. FIVRs are highly configurable, allowing them to power a wide range of products from 3W fanless tablets to 300W servers. FIVR helps enable 50% or more battery life improvements for mobile products and more than doubles the peak power available for burst workloads.

A 480-MHz, multi-phase interleaved buck DC-DC converter with hysteretic control

We propose an on-chip 1.8 V-to-0.9 V DC-DC converter aimed to reduce the input current and decoupling requirements of future microprocessors. By utilizing a 90-nm CMOS process, employing a four-phase hysteretic control, and operating at ultra-high frequency of 480-MHz, we achieved a 10% output droop with only 2.5 nF of on-chip decoupling, for 0.5 A of load current. No off-chip decoupling was connected to the output. At 480 MHz the measured efficiency was 72%. At 250 MHz, the efficiency improved to 76% at the cost of a 17% droop or larger decoupling of 11.5 nF. A converter with 100 A rating would require a capacitor of 0.5 /spl mu/F, which is comparable to the size of an on-chip capacitor of a typical microprocessor.

Integrated on-chip inductors using magnetic material (invited)

On-chip inductors with magnetic material are integrated into both advanced 130 and 90 nm complementary metal-oxide semiconductor processes. The inductors use aluminum or copper metallization and amorphous CoZrTa magnetic material. Increases in inductance of up to 28 times corresponding to inductance densities of up to 1.3 μ H / mm 2 were obtained, significantly greater than prior values for on-chip inductors. With such improvements, the effects of eddy currents, skin effect, and proximity effect become clearly visible at higher frequencies. The CoZrTa was chosen for its good combination of high permeability, good high-temperature stability ( > 250 ° C ) , high saturation magnetization, low magnetostriction, high resistivity, minimal hysteretic loss, and compatibility with silicon technology. The CoZrTa alloy can operate at frequencies up to 9.8 GHz , but trade-offs exist between frequency, inductance, and quality factor. The effects of increasing the magnetic thickness on the permeability spectra were measured and modeled. The inductors use magnetic vias and elongated structures to take advantage of the uniaxial magnetic anisotropy. Techniques are presented to extract a sheet inductance and examine the effects of magnetic vias on the inductors. The inductors with thick copper and thicker magnetic films have resistances as low as 0.04 Ω , and quality factors up to 8 at frequencies as low as 40 MHz.

Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation

Rapidly increasing input current of microprocessors resulted in rising cost and motherboard real estate occupied by decoupling capacitors and power routing. We show by analysis that an on-die switching DC-DC converter is feasible for future microprocessor power delivery. The DC-DC converter can be fabricated in an existing CMOS process (90nm-180nm) with a back-end thin-film inductor module. We show that 85% efficiency and 10% output voltage droop can be achieved for 4:1, 3:1, and 2:1 conversion ratios, area overhead of 5% and no additional on-die decoupling capacitance. A 4:1 conversion results in 3.4/spl times/ smaller input current and 6.8/spl times/ smaller external decoupling.

A 100MHz Eight-Phase Buck Converter Delivering 12A in 25mm2 Using Air-Core Inductors

We present a 100MHz eight-phase synchronous buck converter using air-core inductors. The voltage regulator (VR) chip was manufactured in a 90nm CMOS process and mounted on a flip-chip test package together with surface-mount inductors and decoupling capacitors. The measured peak efficiency is 84.0% for Vin/Vout= 2.4V/1.5V and 79.3% for 2.4V/1.2V. The VR delivers a load current of 12A in an area of only 25mm2 and 2.5mm height. This is the first demonstration of a high-frequency VR with air-core inductors, that reaches a record power density of 3.78kW/in3.

High Voltage Tolerant Linear Regulator With Fast Digital Control for Biasing of Integrated DC-DC Converters

Integrated DC-DC converters switching above 100MHz dramatically reduce the footprint of the inductors and capacitors while improving droop response. Unfortunately, such converters utilize advanced digital CMOS processes with the maximum input voltage below 2 V. We propose a fully integrated linear regulator that enables doubling of the converter input voltage by properly biasing stacked drivers and bridge transistors. By implementing fast digital control the linear regulator meets the transient current demand of the converter without resorting to off-chip decoupling capacitors. In a 90 nm CMOS process, the 2.4V input, 1.2 V output, linear regulator occupies 0.03 mm2 for a plusmn1 A rating. A 288 ps response time and 97.5% current efficiency result in a 2.84times improvement in speed-power figure of merit over previous work

Determination of the line edge roughness specification for 34 nm devices

The impact of gate line edge roughness (LER) on 70 nm MOS devices was measured experimentally and used to validate an enhanced statistical technique for evaluating LER effects on devices. The technique was used to determine that LER in 34 nm devices will need to be limited to 3 nm. Effect of LER spectrum on wide and narrow devices is discussed, as well as an approach for correcting experimental current measurements for LER.