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Dive into the research topics where Fabrice Paillet is active.

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Featured researches published by Fabrice Paillet.


IEEE Transactions on Magnetics | 2009

Review of On-Chip Inductor Structures With Magnetic Films

Donald S. Gardner; Gerhard Schrom; Fabrice Paillet; Brice Jamieson; Tanay Karnik; Shekhar Borkar

A comparison of on-chip inductors with magnetic materials from previous studies is presented and examined. Results from on-chip inductors with magnetic material integrated into a 90 nm CMOS processes are presented. The inductors use copper metallization and amorphous Co-Zr-Ta magnetic material. Inductance densities of up to 1700 nH/mm2 were obtained thanks to inductance increases of up to 31 times, significantly greater than previously published on-chip inductors. With such improvements, the effects of eddy currents, skin effect, and proximity effect become clearly visible at higher frequencies. Co-Zr-Ta was chosen for its good combination of high permeability, good stability at high temperature (> 250degC), high saturation magnetization, low magnetostriction, high resistivity, minimal hysteretic loss, and compatibility with silicon technology. The Co-Zr-Ta alloy can operate at frequencies up to 9.8 GHz, but trade-offs exist between frequency, inductance, and quality factor. Our inductors with thick copper and thicker magnetic films have dc resistances as low as 0.04 Omega, and quality factors of up to 8 at frequencies as low as 40 MHz.


applied power electronics conference | 2014

FIVR — Fully integrated voltage regulators on 4th generation Intel® Core™ SoCs

Edward A. Burton; Gerhard Schrom; Fabrice Paillet; Jonathan P. Douglas; William J. Lambert; Kaladhar Radhakrishnan; Michael J. Hill

Intels® 4th generation Core™ microprocessors are powered by Fully Integrated Voltage Regulators (FIVR). These 140 MHz multi-phase buck regulators are integrated into the 22nm processor die, and feature up to 80 MHz unity gain bandwidth, non-magnetic package trace inductors and on-die MIM capacitors. FIVRs are highly configurable, allowing them to power a wide range of products from 3W fanless tablets to 300W servers. FIVR helps enable 50% or more battery life improvements for mobile products and more than doubles the peak power available for burst workloads.


Journal of Applied Physics | 2008

Integrated on-chip inductors using magnetic material (invited)

Donald S. Gardner; Gerhard Schrom; Peter Hazucha; Fabrice Paillet; Tanay Karnik; Shekhar Borkar; Roy Hallstein; Tony Dambrauskas; Charles Hill; Clark Linde; Wojciech Worwag; Robert Baresel; Sriram Muthukumar

On-chip inductors with magnetic material are integrated into both advanced 130 and 90 nm complementary metal-oxide semiconductor processes. The inductors use aluminum or copper metallization and amorphous CoZrTa magnetic material. Increases in inductance of up to 28 times corresponding to inductance densities of up to 1.3 μ H / mm 2 were obtained, significantly greater than prior values for on-chip inductors. With such improvements, the effects of eddy currents, skin effect, and proximity effect become clearly visible at higher frequencies. The CoZrTa was chosen for its good combination of high permeability, good high-temperature stability ( > 250 ° C ) , high saturation magnetization, low magnetostriction, high resistivity, minimal hysteretic loss, and compatibility with silicon technology. The CoZrTa alloy can operate at frequencies up to 9.8 GHz , but trade-offs exist between frequency, inductance, and quality factor. The effects of increasing the magnetic thickness on the permeability spectra were measured and modeled. The inductors use magnetic vias and elongated structures to take advantage of the uniaxial magnetic anisotropy. Techniques are presented to extract a sheet inductance and examine the effects of magnetic vias on the inductors. The inductors with thick copper and thicker magnetic films have resistances as low as 0.04 Ω , and quality factors up to 8 at frequencies as low as 40 MHz.


applied power electronics conference | 2007

A 100MHz Eight-Phase Buck Converter Delivering 12A in 25mm2 Using Air-Core Inductors

Gerhard Schrom; P. Hazucha; Fabrice Paillet; D. J. Rennie; S. T. Moon; D. S. Gardner; T. Kamik; P. Sun; T. T. Nguyen; Michael J. Hill; Kaladhar Radhakrishnan; T. Memioglu

We present a 100MHz eight-phase synchronous buck converter using air-core inductors. The voltage regulator (VR) chip was manufactured in a 90nm CMOS process and mounted on a flip-chip test package together with surface-mount inductors and decoupling capacitors. The measured peak efficiency is 84.0% for Vin/Vout= 2.4V/1.5V and 79.3% for 2.4V/1.2V. The VR delivers a load current of 12A in an area of only 25mm2 and 2.5mm height. This is the first demonstration of a high-frequency VR with air-core inductors, that reaches a record power density of 3.78kW/in3.


international solid state circuits conference | 2007

High Voltage Tolerant Linear Regulator With Fast Digital Control for Biasing of Integrated DC-DC Converters

Peter Hazucha; Sung Tae Moon; Gerhard Schrom; Fabrice Paillet; Donald S. Gardner; Saravanan Rajapandian; Tanay Karnik

Integrated DC-DC converters switching above 100MHz dramatically reduce the footprint of the inductors and capacitors while improving droop response. Unfortunately, such converters utilize advanced digital CMOS processes with the maximum input voltage below 2 V. We propose a fully integrated linear regulator that enables doubling of the converter input voltage by properly biasing stacked drivers and bridge transistors. By implementing fast digital control the linear regulator meets the transient current demand of the converter without resorting to off-chip decoupling capacitors. In a 90 nm CMOS process, the 2.4V input, 1.2 V output, linear regulator occupies 0.03 mm2 for a plusmn1 A rating. A 288 ps response time and 97.5% current efficiency result in a 2.84times improvement in speed-power figure of merit over previous work


international solid-state circuits conference | 2007

On-Die Supply-Resonance Suppression Using Band-Limited Active Damping

Jianping Xu; Peter Hazucha; Mingwei Huang; Paolo A. Aseron; Fabrice Paillet; Gerhard Schrom; James W. Tschanz; Cangsang Zhao; Vivek De; Tanay Karnik; Greg Taylor

The impedance of a microprocessor power-delivery network peaks at ~140MHz, resulting in power-grid resonance, which lowers operating frequency and compromises reliability. A suppression circuit uses an active-damping technique with a maximum of 12.7dB peak-to-peak noise reduction from 70 to 250MHz in a 90nm CMOS process.


international electron devices meeting | 2006

Integrated On-Chip Inductors with Magnetic Films

Donald S. Gardner; Gerhard Schrom; Peter Hazucha; Fabrice Paillet; Tanay Karnik; Shekhar Borkar; Jason Saulters; Jordan Owens; Jeff Wetzel

On-chip inductors with 2 levels of magnetic material were integrated into an advanced 130-nm CMOS process to obtain over an order of magnitude increase in inductance (19times) and Q-factor (16times), significantly greater than prior values of les2.3times for high frequency inductors. The magnetic material enhances inductance at frequencies up to 9.8 GHz. Measurements and models of the permeability from amorphous CoZrTa alloy demonstrate that the skin effect and eddy current dampening become important. Two levels of magnetic material with high-temperature and long annealing-time stability, high saturation magnetization, low magnetostriction, high resistivity, minimal hysteretic loss, and compatibility with Si technology were used in combination with magnetic vias and elongated structures that take advantage of the uniaxial magnetic anisotropy


international symposium on circuits and systems | 2006

High-frequency DC-DC conversion : fact or fiction

Tanay Karnik; Peter Hazucha; Gerhard Schrom; Fabrice Paillet; Donald S. Gardner

Rapidly increasing input current of microprocessors results in rising cost and motherboard real estate occupied by power delivery system. We show that a high-frequency switching DC-DC converter is feasible in 180nm-90nm technology processes for microprocessor power delivery. The current DC-DC converters on microprocessor motherboards are switching at KHz frequencies because of the strict efficiency requirements. We demonstrate a 480MHz DC-DC converter fabricated in a 90nm CMOS process. We also present measurement results on two high-speed CMOS regulation chips to prove high-frequency conversion is a fact


international solid-state circuits conference | 2006

A Linear Regulator with Fast Digital Control for Biasing Integrated DC-DC Converters

Peter Hazucha; Sung Tae Moon; Gerhard Schrom; Fabrice Paillet; Donald S. Gardner; Saravanan Rajapandian; Tanay Karnik

A high-voltage-tolerant 2.4 to 1.2V push-pull linear regulator with 1A output, 288ps response time, and 97.5% current efficiency for biasing integrated DC-to-DC converters is introduced. The regulator occupies 0.03mm2 in 90nm CMOS and achieves 33A/mm2 current density. Digital control with a flash ADC and a digital-to-current converter improve speed-power performance by 3times


symposium on vlsi circuits | 2015

Broadwell: A family of IA 14nm processors

Ankireddy Nalamalpu; Nasser A. Kurd; Anant Deval; Christopher P. Mozak; Jonathan P. Douglas; Ashish Khanna; Fabrice Paillet; Gerhard Schrom; Boyd S. Phelps

Intel Core™ M and 5th generation of Core™ processors (code named Broadwell) are fabricated on an optimized 14 nm process technology node resulting in a 49% reduction in feature-neutral die area. 14nm created a new optimized process flavor for Core™ M to improve energy efficiency for mobile devices. Techniques and optimizations were implemented to deliver 2.5x TDP reduction coupled with up-to 60% higher graphics performance. New process technology combined with various design techniques reduced the minimum voltage of operation by 50 m V. Broadwell introduces the second generation of Fully Integrated Voltage Regulator with better droop control and parallel boot LVR along with other power-reduction features resulting in 35% reduction in active and standby power over first generation. 3DL inductor technology introduced for the first time in Broadwell, enables 30 % reduction in package thickness and improved low-load efficiency. IO re-partitioning of the SOC and a major re-design of DDR system resulted in 30% reduction in I/O power. Shutting down various parts of the SOC die in various idle states (C* states) resulted in 60% reduction in the idle power. New software controlled co-optimization methods were implemented such as duty-cycle control and dynamic display support to improve the energy efficiency of the graphics and the display subsystem.

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