Gernot Langguth

Transient behavior of SCRS during ESD pulses

Silicon controlled rectifiers (SCRs) are widely used ESD protection elements exhibiting extremely good voltage clamping and high failure current threshold. However, the turn-on behavior of the SCR is often a matter of concern. A detailed transient study of the 3-D current and temperature distribution in a SCR during a high current square pulse is presented leading to design options with shorter delay between trigger point and full clamp performance.

Integrated photodiodes in standard BiCMOS technology

Photodiode structures were integrated in a low cost 0.5 μm silicon BiCMOS process using standard process flow without any technology modification. Rise times of 1.3ns and 1.4ns were measured for wavelengths λ of 660nm and 780nm with a responsivity of 0.23 A/W and 0.14 A/W, respectively. Photodiodes with a high responsivity of 0.42 A/W are reaching a risetime of 4ns for λ = 780nm. Comparable low values for the risetime at 780nm are reported in the literature for integrated photodiodes in standard silicon technologies only with a modification of the epitaxial substrate material. So this photodiodes are suitable for a wide variety of low-cost high-speed optical sensor applications, for optical fiber communication and fiber in home applications.

A self protecting RF output with 2 kV HBM hardness

The present work focuses on the ESD protection of an RF output stage which consists of a fully silicided NMOS stack of mixed device type in a 2.8 V domain. The application of co-design measures improves the ESD hardness from 250 V to 2 kV HBM.

Spice modelling flow for ESD simulation of CMOS ICs

A SPICE based simulation flow is proposed for ESD verification in standard analog simulation environment. Models contain ESD specific sub-circuits and failure thresholds which are activated on demand. Good agreement with experimental data is proven including bipolar operation and the triggering of parasitic paths. The flow has been successfully tested on real designs.

BiCMOS-integrated photodiode exploiting drift enhancement

Abstract. A vertical pin photodiode with a thick intrinsic layer is integrated in a 0.5-μm BiCMOS process. The reverse bias of the photodiode can be increased far above the circuit supply voltage, enabling a high-drift velocity. Therefore, a highly efficient and very fast photodiode is achieved. Rise/fall times down to 94  ps/141  ps at a bias of 17 V were measured for a wavelength of 660 nm. The bandwidth was increased from 1.1 GHz at 3 V to 2.9 GHz at 17 V due to the drift enhancement. A quantum efficiency of 85% with a 660-nm light was verified. The technological measures to avoid negative effects on an NPN transistor due to the Kirk effect caused by the low-doped I-layer epitaxy are described. With a high-energy collector implant, the NPN transit frequency is held above 20 GHz. CMOS devices are unaffected. This photodiode is suitable for a wide variety of high-sensitivity optical sensor applications, for optical communications, for fiber-in-the-home applications, and for optical interconnects.