Krzysztof Domanski

Development strategy for TLU-robust products

Detailed transient latch-up (TLU) analyses of external test structures show that a DC trigger does not necessarily reflect worst case conditions. Furthermore, the classical guard ring latch-up protection approach fails for transient trigger. In this contribution, design recommendations for TLU-safe designs are presented. The knowledge about the perturbation environment and an appropriate design are essential for a TLU-robust product.

Investigation of External Latchup Robustness of Dual and Triple Well Designs in 65nm Bulk CMOS Technology

In this work, the effect of design parameters on the internal and external latchup robustness of dual well (DW) and triple well (TW) test structures designed in 65nm bulk CMOS technology is studied. It is found that while both DW and TW latchup structures were robust for a positive-mode external latchup (latchup trigger current, ITRIG > 200mA), TW latchup structures were more susceptible to negative mode external latchup. The ITRIG for the worst case TW latchup structure was ~50% lower compared to a similarly designed test structure in DW. Isolation of injection sources is more efficient in TW as compared to DW design and can be further improved by appropriate design of I/O devices and guard rings surrounding the I/Os

Transient latch-up: experimental analysis and device simulation

A set-up consisting of at least one pulse generator with baseline functionality was used for Transient Latch-up (TLU) investigations. Dependencies of the TLU sensitivity of test structures on the pulse width and the rise time have been analyzed. Device simulation could reproduce the tendencies and reveals the root cause for the dependencies. In a bipolar product, which is immune against static latch-up, transient latch-up could be triggered, showing clearly the importance of a TLU characterization and the capability of the set-up.

Transient-LU failure analysis of the ICs, methods of investigation and computer aided simulations

With the ongoing technology downscaling transient latch-up (TLU) becomes increasingly important. There is a common understanding that TLU is even a higher risk than the static LU. The comprehensive TLU analysis of three different products in combination with detailed failure analysis and TCAD simulations have been presented in this paper.

SCR operation mode of diode strings for ESD protection

Diodes and diode strings in 90 nm and beyond technologies are investigated by measurement and device simulation. After a thorough calibration, the device simulator is utilised to achieve a better understanding and an enhanced device performance of diode strings under DC and transient ESD conditions. Thereto, parasitic transistors and a so far neglected parasitic thyristor (SCR) in the diode string are exploited and optimised.

External (transient) latchup phenomenon investigated by optical mapping (TIM) technique

Substrate current distribution as trigger for external latchup (LU) and transient latchup (TLU) is detected successfully by means of optical transient interferometric mapping (TIM) technique. The substrate current flow is studied on transient base and for various guard-ring configurations. TIM uncovers proximity effects causing substrate current crowding which are important for the definition of LU protection concepts.

Triggering of Transient Latch-up by System-Level ESD

This paper investigates the influences of temperature and the trigger parameters (width and rise time) on the threshold of transient latch-up (TLU). It is shown that temperature is a much more critical parameter than transient trigger parameters. For high discharge currents which are typical for system-level surges as, e.g., seen in cable discharge events, even very short trigger pulses can cause TLU.

Transient interferometric mapping of carrier plasma during external transient latch-up phenomena in latch-up test structures and I/O cells processed in CMOS technology.

Substrate current distribution as trigger for external latch-up (LU) and transient latch-up (TLU) is analyzed by optical transient interferometric mapping (TIM) technique. The transient free carrier (plasma) concentration related to substrate current flow is studied for various guard-ring configurations and injection carrier type on special test structures and real I/O cells. TIM uncovers proximity effects in I/O cells causing substrate current crowding which are important for the definition of effective LU protection concepts.

Physical fundamentals of external transient latch-up and corrective actions

Detailed transient latch-up (TLU) analysis of external test structures show that a DC trigger does not necessarily reflect worst-case conditions. Furthermore, the classical guard ring latch-up protection approach fails for a transient trigger. In this contribution, the physical mechanism of TLU triggering is presented. The knowledge of physical phenomenons causing TLU triggering enables the derivation of design recommendations for integrated circuits.

Multi-terminal pulsed force & sense ESD verification of I/O libraries and ESD simulations

A multi-terminal TLP measurement technique is used for accessing current and voltage distributions during ESD in typical I/O cell frames in a 0.13 um CMOS technology. The procedure extends traditional I/O library testchip based ESD verification and qualification tests, allows to calibrate ESD chip-level simulation tools and to derive precise I/O library application rules.