John P. Denton

Integrated nanoscale silicon sensors using top-down fabrication

Semiconductor device-based sensing of chemical and biological entities has been demonstrated through the use of micro- and nanoscale field-effect devices and close variants. Although carbon nanotubes and silicon nanowires have been demonstrated as single molecule biosensors, the fabrication methods that have been used for creating these devices are typically not compatible with modern semiconductor manufacturing techniques and their large scale integration is problematic. These shortcomings are addressed by recent advancements in microelectronic fabrication techniques which resulted in the realization of nanowire-like structures. Here we report a method to fabricate silicon nanowires at precise locations using such techniques. Our method allows for the realization of truly integrated sensors capable of production of dense arrays. Sensitivity of these devices to changes in the ambient gas composition is also shown.

Multiple layers of silicon-on-insulator islands fabrication by selective epitaxial growth

This paper presents for the first time, multiple layers of silicon-on-insulator (MLSOI) device islands fabricated using selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO) techniques. MLSOI has the potential for ultra dense device integration. SOI device islands as small as 150 nm/spl times/150 nm, with thickness down to 40 nm have been fabricated. SOI device islands (5 /spl mu/m/spl times/500 /spl mu/m) in the second layer have shown no stacking faults in the 1290 islands inspected. To demonstrate the device quality material, fully depleted SOI (FD-SOI) P-MOSFETs were fabricated in the first layer SOI islands with gate lengths down to less than 170 nm. Typically they had low subthreshold leakage, below 0.2 pA//spl mu/m, and a subthreshold swing of 76 mV/dec was measured.

Multiple layers of silicon-on-insulator for nanostructure devices

A new method for silicon-on-insulator (SOI) is presented that has very few stacking fault defects and produces multiple layers of single crystal silicon surrounded by thermal SiO2. The technique requires selective epitaxial growth, epitaxial lateral overgrowth, and chemical mechanical planarization to form SOI islands stacked in multiple layers. Islands of silicon as small as 150×150×40 nm thick were fabricated. Larger SOI islands in two SOI layers, with grown vertical interconnections between layers, were 5×500×0.1 μm. Only one stacking fault was observed in 85 000 μm2 of the first layer and none in the second layer. P-channel metal–oxide–semiconductor field effect transistors with gate lengths of less than ∼100 nm were fabricated in the thin SOI islands. They had normal current–voltage plot characteristics with less than 0.2 pA/μm of leakage current, illustrating the quality of the material in both SOI layers and at the silicon to thermal-oxide interfaces. The devices had measured subthreshold slopes of...

Precision crystal corner cube arrays for optical gratings formed by (100) silicon planes with selective epitaxial growth

High-quality, micrometer scale, corner cube arrays were grown on (111) silicon substrates by selective epitaxial growth (SEG) techniques. Sixteen different arrays were produced that had periodic corner spacing ranging from 3 to 50 µm. The arrays were formed by suppressing silicon SEG in a regular geometric pattern, producing the three mutually perpendicular (100) smooth crystal planes. For coherent light of 633-nm wavelengtha sharp diffraction pattern of threefold symmetry was observed out to 7 maxima, as well as a retroreflection component.

Reduction of sidewall defect induced leakage currents by the use of nitrided field oxides in silicon selective epitaxial growth isolation for advanced ultralarge scale integration

Defects in the near sidewall region in selective epitaxial growth of silicon have prevented its widespread use as a viable dielectric isolation technology. The main cause of these defects has been demonstrated to be thermal stress due to mismatch in the coefficient of thermal expansion between silicon and silicon dioxide. This article presents the detailed electrical characterization of these sidewall defects using P+/N junction diodes fabricated using silicon dioxide and thermally nitrided silicon dioxide as the field insulator. It is shown that the use of field oxide which was nitrided at 1100 °C for 60 min in ammonia gas ambient reduced the reverse saturation current density in the diodes by a factor of 6 and also improved the forward recombination and ideality factors when compared to standard thermal field oxide isolated diodes. The improvement of the sidewall quality was attributed to a reduction in thermal stress due to the modification of the coefficient of thermal expansion of nitrided silicon oxide.

Elimination of the sidewall defects in selective epitaxial growth (SEG) of silicon for a dielectric isolation technology

Selective epitaxial growth (SEG) of silicon has not had widespread use as a dielectric isolation technology due to the near sidewall defects at the SiO/sub 2//Si interface. These defects are located in the first 1-2 /spl mu/m of the SEG/sidewall SiO/sub 2/ interface. Diode junctions intersecting the sidewall and 5 /spl mu/m removed from the sidewall were fabricated in SEG material using thermally grown silicon dioxide (OX) and thermally nitrided thermal silicon dioxide (NOX) as the field insulating mask. Averaged over 16 devices of each type, diodes fabricated with NOX had much better low current I-V characteristics and minimum ideality factors (1.03) than diodes fabricated with OX field oxides (1.23). Junctions intersecting the NOX field insulator had nearly identical characteristics to bulk SEG.

Fully planar method for creating adjacent ‘‘self‐isolating’’ silicon‐on‐insulator and epitaxial layers by epitaxial lateral overgrowth

A novel and simple process is demonstrated for creating isolated silicon‐on‐insulator (SOI) tubs adjacent to selective epitaxial substrate layers. The process results in a fully planar wafer surface which is uniquely suited for mixed bipolar/complementary metal‐oxide‐semiconductor device fabrication. Low‐temperature epitaxial lateral overgrowth (ELO) using SiH2Cl2/HCl/H2 is carried out in a reduced‐pressure chemical vapor deposition reactor to create SOI islands in thermally grown SiO2 valleys. SOI islands and epitaxial seed regions are ‘‘self‐isolated’’ by chemical‐mechanical planarization. The as‐grown ELO is single‐crystal material with well‐defined facets. Planarized SOI and epilayer regions have planar, featureless surfaces. Defect etching for the nonoptimized SOI layers indicates about 5×104 stacking faults/cm2.

Electrical effects of a single stacking fault on fully depleted thin-film silicon-on-insulator P-channel metal–oxide–semiconductor field-effect transistors

Electrical effects of a single stacking fault on fully depleted thin-film silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) were characterized. A simple method was demonstrated for the fabrication of fully depleted thin-film SOI MOSFETs with a single stacking fault in their channel region. SOI islands were created using selective epitaxial growth/epitaxial lateral overgrowth technology. The influence of a single stacking fault on device I–V characteristics was determined and compared to that of nearby identical devices without stacking faults. Off-state leakage currents, a threshold voltage shift, and drive current lowering were observed for devices with a single stacking fault in their channel region. Based on the location of the single stacking fault relative to the device channel region, various physical models were proposed to explain the phenomena observed.

Nitrided thermal SiO2 for use as top and bottom gate insulators in self-aligned double gate silicon-on-insulator metal–oxide–semiconductor field effect transistor

Nitrided thermal oxide was used to reduce the degradation of top and bottom gate insulators of self-aligned double gate metal–oxide–semiconductor field effect transistors that use a form of selective epitaxial growth of silicon (SEG) called tunnel epitaxy. The degradation of thermal oxide was due to the exposure of gate insulator to the epi-growth ambient gases during the epitaxial growth. Both thermal oxide and thermally nitrided oxide samples were exposed to the epi-reactor gases and then the electrical characteristics were measured. Nitrided oxide showed significantly higher breakdown field, lower leakage current, and lower interface states than the thermal oxide after exposure to the selective epi-growth environment. For a 30 min stress in epi-reactor ambient, thermal oxide showed average breakdown fields of less than 1 MV/cm due to the formation of pinholes, while nitrided oxide samples showed average breakdown fields of 15.6 MV/cm for same stress condition. Interface state density (Dit) of nitrided ...

Selective epitaxial growth of Si1−xGex/Si strained-layers in a tubular hot-wall low pressure chemical vapor deposition system

Selective epitaxial growth (SEG) of SiGe on patterned-oxide silicon substrates, using a tubular hot-wall low pressure chemical vapor deposition (LPCVD) system, has been demonstrated. This conventional LPCVD system was proposed as a low cost alternative for SiGe epitaxial growth. Dichlorosilane (SiH2Cl2) and germane (GeH4) were used as the reactant gases with hydrogen as a carrier gas, with no addition of HCl needed to achieve selectivity in quality epitaxial growth of SiGe. Nomarski microscopy showed good selectivity with no nucleation occurring on the SiO2 areas. A low defect silicon buffer layer grown under SEG conditions was key in obtaining high-quality growth. Cross-sectional transmission electron microscopy showed that the SiGe strained layers grown at 700 °C, 750 °C, and 800 °C were of high quality.