J.P. Denton

Fully depleted dual-gated thin-film SOI P-MOSFETs fabricated in SOI islands with an isolated buried polysilicon backgate

P-channel dual-gated thin-film silicon-on-insulator (DG-TFSOI) MOSFETs have been fabricated with an isolated buried polysilicon backgate in an SOI island formed by epitaxial lateral overgrowth (ELO) of silicon. This structure allows individual operation of both the top and back gates rather than the conventional common backgate structure. When fully-depleted, the buried gate is used to individually shift the top gate threshold voltage (V/sub T/). A linear shift of /spl Delta/V/sub T,top///spl Delta/V/sub G,back/ of 0.5 V/V was achieved with a thin buried oxide. The effective density of interface traps (D/sub it/) for the backgate polysilicon-oxide SOI interface was measured to be 1.8/spl times/10/sup 11/ #/cm/sup 2//spl middot/eV as compared to the substrate-oxide of 1.1/spl times/10/sup 11/ #/cm/sup 2//spl middot/eV.

Unique method to electrically characterize a single stacking fault in silicon-on-insulator metal–oxide–semiconductor field-effect transistors

A unique and simple method is demonstrated for characterizing the electrical behavior of a single stacking fault in thin-film fully depleted silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistors (MOSFETs). SOI islands were created using selective epitaxial growth/epitaxial lateral overgrowth technology. P-channel MOSFETs, with the presence of a single stacking fault entirely in the channel region, were measured. The influence of a single stacking fault on device current–voltage characteristics was determined and compared to that of nearby identical devices without stacking faults. It was found that the threshold voltage increased and saturation current decreased, but had low subthreshold leakages. P-channel MOSFETs, with a single stacking fault crossing the gate and penetrating into the source and drain, had high subthreshold leakage currents.

A polysilicon contacted subcollector BJT for a three-dimensional BiCMOS process

A polysilicon contacted subcollector (PCS) bipolar junction transistor (BJT) was fabricated using selective epitaxial growth (SEG) of silicon to form the active region. The fabrication is the first step in the development of a novel 3-D BiCMOS process. To study the efficacy of the polysilicon collector contact, three types of BJTs were fabricated and their collector resistances were compared. These were the PCS BJT, a BJT fabricated in SEG silicon grown from a shallow trench incorporating a shallow collector contact with a buried layer, and a BJT fabricated in the silicon substrate with a shallow collector contact but no buried layer. The PCS BJT exhibited the smallest collector resistance as well as excellent device characteristics, demonstrating its viability for a 3-D BiCMOS process.<<ETX>>

Stacking fault reduction in Silicon-on-Insulator (SOI) islands produced by Selective Epitaxial Growth (SEG) of Silicon using a thermally nitrided SiO2 field insulator☆

Abstract A method to fabricate silicon-on-insulator (SOI) device sized islands, using Epitaxial Lateral Overgrowth (ELO) from the Selective Epitaxial Growth (SEG) of Silicon, has ≈96.3% stacking fault-free SOI islands when SiO 2 was used as the field insulator. When a nitrided thermal SiO 2 was used ≈99% of the small islands were defect-free. Islands with rounded corners and nitrided oxide had stacking fault defects of less than 500/cm 2 .

Fully depleted dual-gated thin-film SOI p-MOSFET with an isolated buried polysilicon backgate

A p-channel Dual-Gated Thin-Film Silicon-on-insulator (DG-TFSOI) MOSFET has been fabricated with an isolated buried polysilicon backgate and is in a SOI island. This structure allows individual operation of each backgate of each device, rather than the present common backgate (substrate) structure. The ability to use a individual buried gate to dynamically shift the threshold voltage of each individual top MOSFET may have significant implications for low power circuits and offers a way to boost drive currents for faster switching. By using Epitaxial Lateral Overgrowth (ELO) the bottom thermal buried oxide can be specified to any thickness.

Silicon-on-insulator processes for the fabrication of novel nanostructures

In this brief report, we discuss novel single crystal structures for electronic device and microelectromechanical system applications using processes that employ selective epitaxial growth (SEG) and silicon-on-insulator (SOI) wafers. Selective epitaxial growth of silicon is used to provide robust, reliable mechanical and electrical contacts between the SOI layer and the substrate. Subsequent removal of the buried oxide results in single crystal structures suspended in air. The films can then be thinned using wet or dry etching or thinned using sacrificial oxidation steps with the possibility of forming ultrathin SOI layers. Diodes formed at the substrate–SEG junction demonstrate high breakdowns and low leakage indicating good electrical isolation between the SOI layer and the substrate. The silicon on air regions can be used for dual-gate metal–oxide–semiconductor devices, quantum wires, cantilevers, as a substrate for lattice mismatched epitaxy, ultrathin SOIs, and lateral field emission tips.

Degradation of insulators in Silicon Selective Epitaxial Growth (SEG) ambient

The degradation of various insulators in Silicon Selective Epitaxial Growth (SEG) ambient was studied. The insulators studied were thermal oxide, reoxidized nitride/oxide stack, poly-oxide, and nitrided oxide. Breakdown electric fields of MIS capacitors were measured and yields were calculated before and after the insulators were exposed to Silicon SEG ambient. It was found that the nitrided oxide was more resistant to degradation in the SEG ambient than thermal and poly oxide; results reported here for the first time. The increased resistance of nitrided oxide in SEG ambient coupled with their superior performance as thin gate insulators makes them an excellent candidate for use in novel 3-D structures using selective silicon growth.<<ETX>>

A fully integrable insulated gate bipolar transistor with a trench gate structure

A novel, fully integrable insulated gate bipolar transistor (IGBT) with a trench gate structure, called the 3D IGBT, is described. The 3D IGBT uses selective epitaxial silicon to form a top-contacted anode and still retain the cellular structure of vertically oriented devices. It is fabricated using a self-aligned process that permits an increase in channel density by reducing the trench width. Two-dimensional computer simulations of 3D IGBTs with a unit cell width of 15 mu m have been performed and show an increase in channel density by a factor of more than eight over the lateral IGBT.<<ETX>>

Thin-film silicon-on-insulator (SOI) device applications of selective epitaxial growth

Silicon-on-insulator (SOI) technology has surged into a position of prominence in recent years. SOI devices provide a viable technology for high-density, large-scale-integration and high performance VLSI circuits. Of late, the potential applications of SOI devices have extended to the field of power devices and mixed-mode analog-digital circuits. In this field of application in particular, selective epitaxial growth techniques such as epitaxial lateral overgrowth (ELO) and Confined Lateral Selective Epitaxial Growth (CLSEG) provide attractive alternatives to SIMOX. ELO and CLSEG provide the means of selectively growing SOI islands in regions where high performance digital MOS circuitry are desired. Due to the low temperatures involved in selective epitaxy, mixed mode integration becomes a lot easier. This paper presents results from fully-depleted SOI devices fabricated by ELO and provides for the first time a study of interface state densities across the various interfaces in the device. In addition, thin-film fully-depleted SOI devices have been fabricated for the first time in SOI device islands fabricated by CLSEG, and the devices have been used to characterize the material.<<ETX>>

Nitrided thermal SiO/sub 2/ for thin buried gate insulators in dual gate SOI-MOSFET

Nitrided thermal oxide (NOX) was used for reducing the degradation of a buried gate insulator during the fabrication of dual-gate Silicon-on-Insulator MOSFETs. The degradation was due to the exposure of the buried gate oxide to the epitaxial growth ambient. Nitridation of thermal SiO/sub 2/, resulted in a robust pinhole-free insulator after selective epitaxial growth of silicon (SEG) allowing for thinner buried gate insulators. A dual-gated fully-depleted SOI-MOSFET was fabricated with a 21.4 nm buried NOX gate and had a dynamic threshold voltage shift of /spl Delta/V/sub T,tap///spl Delta/VC/sub G,huck/=476 mV/V for submicron devices and as high as 550 mV/V for larger devices. Nitridation of the oxide had other benefits, such as reducing thermal-induced stress in the SEG and lowering the near sidewall defects at the SiO/sub 2//Si interface.