Geum-Jong Bae

A novel SiGe-inserted SOI structure for high performance PDSOI CMOSFETs

A novel partially-depleted silicon-on-insulator (PDSOI) CMOSFETs with SiGe-inserted layer have been proposed. The SiGe-inserted layer in NMOS successively suppresses the floating body effects (FBE) by lowering the body-to-source potential barrier to hole current. It also provides a good current performance in PMOS by inducing the change of channel dopant distribution and increasing the efficiency of pocket ion implantation. Consequently, SiGe-inserted SOI devices achieve higher drain-to-source breakdown voltage in NMOS due to the suppression of FBE and increase drive currents of both NMOS and PMOS by 10% and 15%, respectively, compared to conventional PDSOI devices.

Highly manufacturable SONOS non-volatile memory for the embedded SoC solution

A new Local SONOS structure has been proposed for an embedded NVM cell in 0.13 /spl mu/m standard CMOS logic process. The localized storage silicon nitride layer of Local SONOS cell provides the essential properties for the embedded NVM such as the complete erase, low program current, and high on cell current from the low threshold voltage. The entire embedded memory solution has been realized with 0.276 /spl mu/m/sup 2/ Local SONOS NVM cell, which has 20 /spl mu/s program and 2 ms erase speed under 5.5 V bias condition, and good reliability without the special algorithms and cell array modifications.

A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limit. Multi-workfunction (WF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by channel dopants.

50nm gate length logic technology with 9-layer Cu interconnects for 90nm node SoC applications

A 90 nm generation logic technology with Cu/low-k interconnects is reported. 50 nm transistors are employed using gate oxide 1.3 nm in thickness and operating at 1.0 V. High speed transistors have drive currents of 870 /spl mu/A/pm and 360 /spl mu/A//spl mu/m for NMOS and PMOS respectively, while generic transistors have currents of 640 /spl mu/A//spl mu/m and 260 /spl mu/A//spl mu/m respectively. Low power process using high-k gate dielectrics and SOI process are also provided in this technology. The low-k SiOC material with 2.9 in the k value is used for 9 layers of dual damascene Cu/low-k interconnects. The effective k (k/sub eff/) value of interconnect is about 3.6. Fully working 6-T SRAM cell with an area of 1.1 /spl mu/m/sup 2/ and SNM value of 330 mV is obtained. For MIM capacitor, voltage coefficient of capacitance is less than 20 ppm/V.

Improved 1/f Noise Characteristics in Locally Strained Si CMOS Using Hydrogen-Controlled Stress Liners and Embedded SiGe

This paper reports the first experimental demonstration of improved 1/f noise characteristics in a locally strained Si MOS through hydrogen-controlled stress liners and embedded SiGe (eSiGe). For NMOS, the high hydrogen density (1times1022cm-3) in the stress liner results in three times more noise than that of PMOS. For PMOS, eSiGe proves to be superior to a compressive stress liner in noise due to the low hydrogen density in the system. The controlled stress does not generate interface states or other scattering centers, which increase noise, and only improves 1/f noise due to carrier mass reduction

A novel tensile Si (n) and compressive SiGe (p) dual-channel CMOS FinFET co-integration scheme for 5nm logic applications and beyond

A novel tensile Si (tSi) and compressive SiGe (cSiGe) dual-channel FinFET CMOS co-integration scheme, aimed at logic applications for the 5nm technology node and beyond, is demonstrated for the first time, showing electrical performance benefits and excellent co-integration feasibility. A Strain-Relaxed SiGe Buffer (SRB) layer is introduced as buried stressor and successfully transfers up to ∼1 GPa uniaxial tensile and compressive stress to the Si/SiGe n-/p-channels simultaneously. As the result, both tSi and cSiGe devices show a 40% and 10% electron and hole mobility gain over unstrained Si, respectively. Through a novel gate stack solution including a common interfacial layer (IL), HK, and single metal gate for both n- and pFET, secured process margin for 5nm gate length, low interface trap density (Dit) for SiGe channel and threshold voltage (Vt) target for both the Si and SiGe device are successfully demonstrated. Lastly, reliability investigation shows that tSi and cSiGe, employing the newly developed common gate stack scheme, possess superior reliability characteristics compared with those of equivalent Si devices.

Ge-redistributed poly-Si/SiGe stack gate (GRPSG) for high-performance CMOSFETs

A Ge-redistributed poly-Si/SiGe stack gate (GRPSG) has been proposed to improve the current performance of PMOS without the degradation of NMOS for sub-0.1 /spl mu/m CMOSFETs with ultrathin gate oxide. Ge diffusion into the poly-Si layer was promoted more by ion implantation of N-type dopants such as P and As rather than P-type dopants. NMOS and PMOS had different Ge concentrations at the interface between gate electrode and gate oxide by an additional anneal to redistribute the Ge profile. The current performance of NMOS with GRPSG with low Ge content (<5%) was not degraded, while that of PMOS with GRPSG with high Ge content (>20%) was improved due to suppression of the poly-depletion effect and boron penetration. In addition, the gate reoxidation was modified to reduce G/sub m/ degradation by reduced gate birds beak. High-performance 70 nm-CMOSFETs were successfully fabricated using the simple GRPSG process.

10nm FINFET technology for low power and high performance applications

In this paper, we present a 10nm CMOS platform technology for low power and high performance applications with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrates. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limits. Multi-workfunction (MWF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by Random Dopant Fluctuation (RDF) from channel dopants.

Full integration and characterization of Localized ONO Memory (LONOM) for embedded flash technology

We have successfully integrated 8M bits Localized ONO Memory (LONOM) for the embedded nonvolatile memory using 0.13um standard logic process with 5-level Cu metallization. which has a small cell size of 0.276UM and the simplest cell array structure. Without any special algorithm, the localized storage layer of the LONOM can satisfy the essential features for an embedded memory solution, such as low program current. disturb-free read operation and good endurance characteristics. The read speed is as high as 60MHz at V/sub cc/=0.9V, 85/spl deg/C and the current consumption is lower than 5mA at Vcc = 1.4V.

The drive currents improvement of FDSOI MOSFETs with undoped Si epitaxial channel and elevated source/drain structure

Fully-depleted silicon-on-insulator (FDSOI) MOSFETs are very attractive for low-voltage applications due to ideal subthreshold slope, short channel effect (SCE) immunity and reduced junction capacitance compared to bulk silicon MOSFETs. However, the channel mobility degradation due to higher channel doping for threshold voltage (V/sub th/) adjustment and higher source-drain resistance (R/sub sd/) are critical issues for FDSOI MOSFETs with top silicon thickness of less than 50 nm (Wong et al, 1998; Su et al, 1993). It has been reported that an undoped Si epitaxial channel (UEC) of the bulk MOSFETs and elevated source/drain (E-S/D) structures of the FDSOI MOSFETs are very effective for improvement of channel mobility and a low R/sub sd/, respectively (Yan et al, 1992; Kircher et al., 1992; Cao et al., 1997). In this paper, we propose the implementation of UEC for only nMOSFETs and the E-S/D structure for both n- and pMOSFETs to improve drive currents.