Kyungwook Lee

A novel CMP method for cost-effective bonded SOI wafer fabrication

The BOnded Silicon On Insulator (BOSOI) has been considered as a promising substitute for bulk silicon technology because of its structural flexibility. However,there are considerable drawbacks if epitaxial etch stopping or localized plasma etching technique is used in the fabrication process because of low throughput and high cost. In order to obtain the ultrathin SOI layer with uniform thickness, this paper describes the cost-effective fabrication method of bonded SOI wafer using the double step CMP method in which the abrasive concentration of slurry is controlled to enhance the polish throughput. In this technique, a low total thickness variation (TTV) wafer is used as a handle wafer and the thickness variation of SOI layer can be easily reduced within a reasonable polishing time if the abrasive concentration of slurry is properly adjusted.

The drive currents improvement of FDSOI MOSFETs with undoped Si epitaxial channel and elevated source/drain structure

Fully-depleted silicon-on-insulator (FDSOI) MOSFETs are very attractive for low-voltage applications due to ideal subthreshold slope, short channel effect (SCE) immunity and reduced junction capacitance compared to bulk silicon MOSFETs. However, the channel mobility degradation due to higher channel doping for threshold voltage (V/sub th/) adjustment and higher source-drain resistance (R/sub sd/) are critical issues for FDSOI MOSFETs with top silicon thickness of less than 50 nm (Wong et al, 1998; Su et al, 1993). It has been reported that an undoped Si epitaxial channel (UEC) of the bulk MOSFETs and elevated source/drain (E-S/D) structures of the FDSOI MOSFETs are very effective for improvement of channel mobility and a low R/sub sd/, respectively (Yan et al, 1992; Kircher et al., 1992; Cao et al., 1997). In this paper, we propose the implementation of UEC for only nMOSFETs and the E-S/D structure for both n- and pMOSFETs to improve drive currents.