Ghaith Bany Hamad

Characterizing, modeling, and analyzing soft error propagation in asynchronous and synchronous digital circuits

Abstract Soft errors, due to cosmic radiations, are one of the major challenges for reliable VLSI designs. In this paper, we present a symbolic framework to model soft errors in both synchronous and asynchronous designs. The proposed methodology utilizes Multiway Decision Graphs (MDGs) and glitch-propagation sets (GP sets) to obtain soft error rate (SER) estimation at gate level. This work helps mitigate design for testability (DFT) issues in relation to identifying the controllable and the observable circuit nodes, when the circuit is subject to soft errors. Also, this methodology allows designers to apply radiation tolerance techniques on reduced sets of internal nodes. To demonstrate the effectiveness of our technique, several ISCAS89 sequential and combinational benchmark circuits, and multiple asynchronous handshake circuits have been analyzed. Results indicate that the proposed technique is on average 4.29 times faster than the best contemporary state-of-the-art techniques. The proposed technique is capable to exhaustively identify soft error glitch propagation paths, which are then used to estimate the SER. To the best of our knowledge, this is the first time that a decision diagram based soft error identification approach is proposed for asynchronous circuits.

New Insights Into the Single Event Transient Propagation Through Static and TSPC Logic

An investigation of the Single Event Transient (SET) characteristics (amplitude and width) variation while propagating through static and True Single Phase Clock (TSPC) logic is presented. The dependencies of the SET characteristics on the input patterns, propagation paths, pulse polarity, diverging paths, and re-converging paths are investigated. New insights on the propagation induced pulse broadening (PIPB) phenomenon in different combinations of static and TSPC logic are reported. The worst and the best propagation paths for SET pulse broadening and attenuation are identified. Our results demonstrate that SET pulses propagation can lead to Byzantine faults as they propagate through diverging paths. A new way to abstract all possible interpretations of the SET induced Byzantine fault phenomenon is proposed.

Modeling, analyzing, and abstracting single event transient propagation at gate level

Soft errors have become one of the most challenging issues that impact the reliability of modern microelectronic systems at terrestrial altitudes. A new methodology to abstract, model, and analyze Single Event Transient (SET) propagation at different abstraction levels (transistor and gate level) is proposed. Transistor level characterization libraries are developed to abstract the impact of input patterns, pulse polarity, and propagation paths characteristics on the SET duration. Thereafter, these libraries are utilized to analyze SET pulse propagation at gate level using MDG model checker. We have implemented the proposed method on different ISCAS85 benchmark combinational circuits. The proposed methodology is orders of magnitude faster than circuit level simulations. Moreover, we have developed gate level characterization libraries to abstract SET pulse propagation behavior at the gate level.

Efficient and accurate analysis of single event transients propagation using SMT-based techniques

This paper presents a hierarchical framework to model, analyze, and estimate digital design vulnerability to soft errors due to Single Event Transients (SETs). A new SET propagation model is proposed. This model simultaneously includes the impact of masking effects, width variation, and re-converging paths by utilizing satisfiability modulo theories. Furthermore, new metrics characterizing the soft error rate of a given design are proposed. Reported results show that the proposed methodology significantly enhances the efficiency of SET analysis in terms of: 1) accuracy as it gives accurate estimates of SET sensitivity based on gates timing extracted from layout. These results provide new insights to combinational designs vulnerability to SETs; 2) speed as it is orders of magnitude faster than contemporary techniques; 3) scalability as it can handle large and complex designs such as 128-bit multipliers, whereas contemporary techniques are unable to handle multipliers larger than 32 bits.

Efficient multilevel formal analysis and estimation of design vulnerability to Single Event Transients

The progressive shrinking of device size in advanced technologies leads to miniaturization and performance improvements. However, ultra-deep sub-micron technologies are more vulnerable to soft errors. Error analysis of a complex system with a sufficiently large sample of vulnerable nodes takes a large amount of time. In this paper we propose RASVAS, a hierarchical statistical method to model, analyze, and estimate the behavior of a system in the presence of Single Event Transients (SETs) modeled at different abstraction levels. Gate level propagation tables are developed to abstract SET propagation conditions and probabilities from gate level models. At RTL, these tables are utilized to model the underlying probabilistic behavior as Markov Decision Process (MDP) models. Experimental results demonstrate that RASVAS is orders of magnitude faster than contemporary techniques and also handle designs as large as 256-bit adders while maintaining accuracy.

Efficient probabilistic fault tree analysis of safety critical systems via probabilistic model checking

The cost and complexity involved in the development of critical systems encourage the use of reliability assessment techniques as early in the design cycle as possible. Existing techniques often lack the capacity to perform a comprehensive and exhaustive analysis on complex redundant architectures, leading to less than optimal risk evaluation. This paper addresses these weaknesses by 1) proposing a new probabilistic modeling of Fault Tree gates and their composition as Markov Decision Processes; 2) developing a new formal-based technique to perform an in-depth verification of the system’s reliability. This technique makes use of the expressiveness of fault trees and the power of probabilistic model checking in order to investigate the best Triple Modular Redundancy partitioning and configuration of a system. The presented approach greatly improves the overall scalability with respect to other techniques, while also improving the accuracy of the results. For example, we can provide probabilistic failure rates for a chain of 100 redundant components in little over one second.

Abstracting Single Event Transient characteristics variations due to input patterns and fan-out

Due to shrinking feature sizes and significant reduction in noise margins, as CMOS technologies evolve toward ultra-deep sub-micron, digital circuits have become more susceptible to soft errors. Therefore, researchers have recently reported several approaches to model Single Event Transient (SET) propagation at gate or higher abstraction levels. However, contemporary techniques model only the possibility that SET pulse may be masked electrically, logically, or by time windowing. In this paper, the propagation induced pulse broadening (PIPB) phenomenon is further investigated and a new model which abstracts this phenomenon is proposed. This paper also investigates and abstracts the impact of input patterns and propagation paths on SET pulse width. Through electrical simulations, we validated our analysis.

Probabilistic model checking of single event transient propagation at RTL level

Soft errors, induced by radiations, have a growing impact on the reliability of CMOS integrated circuits. The progressive shrinking of device sizes in advanced technologies leads to miniaturization and performance improvements. However, ultra-deep sub-micron technologies are more vulnerable to soft errors. In this paper, we propose a new methodology to model and analyze Single Event Transients (SETs) propagation at RTL level. Gate level characterization libraries are utilized to model the underlying probabilistic behavior of SET pulse propagation as Probabilistic Automata (PA). A probabilistic model checker is adapted to analyze the probability of SET pulse propagation for all injection scenarios. Experimental results are presented for different combinational circuits. Our proposed methodology is orders of magnitude faster than contemporary techniques that can be used to analyze SET pulse propagation probability.

SEGP-Finder: Tool for identification of Soft Error Glitch-Propagating paths at gate level

An increase in vulnerability to soft errors has affected the reliability of both synchronous and asynchronous nanometer scale integrated circuits. Hence in such circuits there is a growing need to identify the soft error glitch propagation possibility before their physical design implementation. This paper proposes a new tool, the Soft Error Glitch-Propagating path Finder (SEGP-Finder), able to analyze the propagation of soft errors at gate level. In SEGP-Finder, soft error modeling is accomplished via Multiway Decision Graphs (MDGs) and Glitch Propagation sets (GP sets). To demonstrate the effectiveness of our tool, several ISCAS89 sequential benchmark circuits, 4-bit and 8-bit adders, 4-bit multiplier, and the Self-timed multiple-group pipeline asynchronous handshake circuit have been analyzed. Results indicate that SEGP-Finder is on average more than 5 times faster, without compromising on the accuracy, in comparison with simulation-based and SAT (satisfiability analysis) based techniques.

Investigating the efficiency and accuracy of a data type reduction technique for soft error analysis

The progressive scaling of semiconductor technologies has led to significant performance improvements in digital designs. However, ultra-deep sub-micron technologies have increased the vulnerability of VLSI designs to soft errors. It is crucial to analyze this vulnerability early in the design process. In this paper we propose a new technique to model, analyze and estimate the propagation of Single Event Upsets (SEUs) in combinational designs at the Register Transfer Level (RTL) using Satisfiability Modulo Theories (SMT). The propagation of SEUs through RTL bit-vector constructs is modeled as a Satisfiability problem using the SMT theory of bit-vectors. Two different analysis techniques, concrete and abstract modeling, are used in order to investigate the efficiency and accuracy of a data type reduction technique for soft error analysis. Concrete modeling uses two versions of the design, one faulty and one fault-free, in order to analyze SEU propagation. Abstract modeling uses data type reduction to evaluate the difference in performance and accuracy over the first method. Experimental results demonstrate that the loss in accuracy due to abstract modeling depends on the design behavior. For example, for some circuits, the loss in accuracy was arround 73%, while for other circuits it was as low as 0.03%. However, abstract modeling allows reducing processing time significantly and an average reduction factor of 3.88 is reported.