Ghazi Bouzid

An 863-870MHz spread-spectrum FSK transceiver design for wireless sensor

Simulation results of a 863-870-MHz frequency-hopped spread-spectrum transceiver with binary frequency shift keying (BFSK) modulation at 20 kb/s for wireless sensor applications is presented. The transmit/receive RF front end contains a BFSK modulator, an up conversion mixer, a power amplifier (PA), and an 863-870 MHz band pass filter (BPF) at the transmitter side and a low-noise amplifier with down conversion mixer to to zero IF, a low-pass channel-select filter, a limiter and a BFSK demodulator at the receiver side. The various blocks parameters of the transmit/receive RF front end like noise figure (NF), gain, 1 dB compression point (P-1dB)and IIP3 are simulated and optimized to meet transceiver specifications. The receiver simulations show 51.1 dB conversion gain, -7 dBm IIP3, -15 dB return loss (S11) and 10 dB NF. The transmitter simulations show an output ACPR (adjacent channel power ratio) of -22 dBc, 3.3 dBm P-1dB of PA and transmitted power of 0 dBm. The transceiver simulations show an RMS frequency error of 1.45 Khz.

FPGA implementation of FHSS-FSK modulator

This In this paper, we present the Binary Frequency Shift Keying (BFSK) modulator using the Frequency Hopping Spread Spectrum (FHSS) operating in the European band ISM 863-870 MHz. This modulator is intended for short range wireless applications, such as the wireless network sensors. The modulator generates a 7 MHz wide single-sideband, frequency hopped spread spectrum waveform for wireless transmission in the 863-870 MHz. This modulator is designed using the Direct Digital Frequency Synthesizer (DDFS) which enables us to generate BFSK signal with the hopping frequencies. Low power DDFS architecture is presented. It uses a smaller lookup table for sine and cosine functions compared with existing systems using a minimum additional hardware. A DDFS with -88 dBc spectral purity, 41.29 Hz frequency resolution and 10 bits output data for sine function generation is being implemented in an FPGA.

Design of a zero crossing BFSK demodulator for a wireless sensor

In this paper, a transistor-level simulation result of a Zero crossing BFSK demodulator is presented. The detector will be integrated into a frequency-hopped spread spectrum receiver operating in the 863-870 MHz ISM band, using the zigbee protocol (IEEE 802.15.4). This end to demodulate a received bit sequence with a bit rate equal to 20 kbps using 0.35 μm CMOS technology and a 3 V power supply. The proposed demodulator dedicated to an application of low power and low cost can maintain good performance under process variation. The BER results show that the proposed demodulator needs only 10.9 dB input signal_to_noise ratio to achieve a BER of 10-3 as specified in zigbee standard.

A 863–870-Mhz spread-spectrum FSK transceiver design for wireless sensor

Simulation results of a 863-870-MHz frequency-hopped spread-spectrum transceiver with binary frequency shift keying (BFSK) modulation at 20 kb/s for wireless sensor applications is presented. The transmit/receive RF front end contains a BFSK modulator, an up conversion mixer, a power amplifier (PA), and an 863-870 MHz band pass filter (BPF) at the transmitter side and a low-noise amplifier with down conversion mixer to to zero IF, a low-pass channel-select filter, a limiter and a BFSK demodulator at the receiver side. The various blocks parameters of the transmit/receive RF front end like noise figure (NF), gain, 1 dB compression point (P-1dB)and IIP3 are simulated and optimized to meet transceiver specifications. The receiver simulations show 51.1 dB conversion gain, -7 dBm IIP3, -15 dB return loss (S11) and 10 dB NF. The transmitter simulations show an output ACPR (adjacent channel power ratio) of -22 dBc, 3.3 dBm P-1dB of PA and transmitted power of 0 dBm. The transceiver simulations show an RMS frequency error of 1.45 Khz.

A 3–5 GHz fully differential power amplifier for low power medical applications

This paper presents the design of a CMOS UWB power amplifier operating in the 3-5 GHz frequency range. The proposed circuit is based on a fully differential topology performing in AB-class to achieve a better linearity and using a bandpass filter network with a shunt feedback technique to obtain wideband matching and flat gain. The design was performed using 0.18 μm technology and simulations results showed a flat power gain of 15.5±0.4 dB across 3-5 GHz band frequency, good input and output return losses with S11 and S22 below -13dB both and excellent phase linearity with a group delay of 18.4 ps while consuming only 25.46 mW from 1.8 V dc, supply.

Design of Ultra Wideband oscillator in 0.18 μm standard CMOS technology

This paper describes the design of a 3-5 GHz oscillator for Impulse-Radio Ultra-Wideband (IR-UWB) transceiver in the 0.18 μm CMOS technology. The most important specifications for the voltage control oscillator (VCO) are provided and architecture for an existing frequency plan is introduced along with a discussion on its performance and implementation. The simulated VCO can achieve very wide tuning range along with low phase noise performance that varies from -92.02 dBc/Hz to -73 dBc/Hz at 1 MHz frequency offset from the carrier and the overall power consumption is 18.1 mW from a 1.8V voltage supply.

A Novel MICS Receiver with FSK Dual Band Demodulator

A R T I C L E I N F O A B S T R A C T Article history: Received: 23 July, 2018 Accepted: 31 August, 2018 Online: 18 September, 2018 A low-complexity dual-band chirp FSK, direct conversion receiver is described in this paper. The receiver is dedicated to be used in the transceiver unit of a medical implantable wireless sensor. The system uses the RF band between 402 and 405 MHz. Two sub-bands frequencies employing chirped pulses are assigned for both binary information. The novelty of this work is the use of a Binary FSK LFM modulator, a direct conversion receiver and a simple and low power non-coherent BFSK envelope detection demodulator. Receiver performances are evaluated for all the input power dynamic range. Receiver front-end parameters are optimized using harmonic balance simulation. In order to improve receiver sensitivity, a low pass filter with controllable bandwidth between 40 and 300 KHz is used to avoid in-band interference. The receiver is able to achieve a noise figure of 5.5 dB, a receiver sensitivity of -93 dBm and a maximum data rate of 100Kbps. The simulated IIP3 and P-1dB are 12.6 dBm and 22.1 dBm respectively. A simple non coherent binary dual band FSK demodulator was used which is based on an envelope detector, integrate & dump, a sampling & hold and a liming circuit. The receiver was co-simulated with the dual band non coherent demodulator. The proposed receiver has a sensitivity of -93 dBm and a BER less than 10.

Improvement of the linearity and conversion gain of an ultra wideband up-conversion mixer in CMOS 0.18 μm technology

This paper presents a fully differential, low power and low voltage UWB up-conversion mixer, operating in the third channel of the ultra wideband range frequency (3-5GHz). Designed on CMOS 0.18 um technology and a voltage supply of 1.8, this circuit is based on a double balanced Gilbert topology, which uses a current injection method to increase the conversion gain and pi-inter-stage matching network formed of additional inductors to improve the linearity. Thus the mixer exhibits 10 dB conversion gain, 10 dBm IP3, a DC power in the range of 4.3 mW and can output an RF signal over the third channel of the low band (3-5) GHz frequency range.

3.1–5GHz IEEE 802.15.4a impulse radio UWB receiver specifications

IEEE 802.15.4a standard targets low data-rate wireless networks with extensive battery life and very low complexity. It has introduced impulse radio ultra-wideband (IR-UWB) as an emerging physical layer for energy-efficient communications. Low-power implementation of the digital baseband processing is critical for the design of an IR-UWB receiver. Thus high speed analog to digital converters (ADC) is needed. This paper presents link radio budget analysis of the receiver. Then ADC parameters needed for the design has been computed. We conclude that 3 bits Flash ADC presents the basic choice that provide sufficient resolution and high sampling rate required for the presented UWB receiver.