Mohamed Masmoudi

Comparative analysis of accelerated ageing effects on power RF LDMOS reliability

We present in this paper results of comparative reliability study of three accelerated ageing tests applied on power RF LDMOS: Thermal Shock Tests (TST, air-air test), Thermal Cycling Tests (TCT, air-air test) and High Temperature Storage Life (HTSL). The two first tests are carried out with a drain current flowing through the device during stress. The results obtained show the variation and the Devices performance quantitative shifts for some macroscopic electric parameters such as threshold voltage (V th ), transconductance (G m ), drain-source current (I ds ), on-state resistance (R ds on) and feedback capacitance (C rs ) tinder various ageing tests. To understand the degradation phenomena that appear after ageing, we used a new electro-thermal model implemented in Agilents ADS as a reliability tool.

Study of RF N− LDMOS critical electrical parameter drifts after a thermal and electrical ageing in pulsed RF

An innovative reliability test bench dedicated to RF power devices is currently implemented. This bench allows to apply both electric and thermal stress for lifetime test under radar pulsed RF conditions. This paper presents the first investigation findings of critical electrical parameter degradations after thermal and electrical ageing. It shows that the tracking of a set of parameters (drain–source current, on-state resistance, threshold voltage, feedback capacitance and

A 5000 h RF life test on 330 W RF-LDMOS transistors for radars applications

A reliability test bench dedicated to RF power devices is used to improve 330 W LDMOS in a radar conditions. The monitoring of RF power, drain, gate voltages and currents under various pulses and temperatures conditions are investigated. Numerous duty cycles are applied in order to stress LDMOS. It shows with tracking all this parameters that only few hot carrier injection phenomenon appear with no incidence on RF figures of merit (Pout or PAE). Robustness and ruggedness are shown for LDMOS with this bench for radar applications in L-band.

Hot carrier reliability of RF N- LDMOS for S Band radar application

Abstract This paper presents an innovative reliability bench specifically dedicated to high RF power device lifetime tests under pulse conditions for radar application. A base-station dedicated LDMOS transistor has been chosen for RF lifetests and a complete device electric characterization has been performed. A whole review of its critical electrical parameters after accelerated ageing tests is proposed and discussed. This study tend to explain the physical degradation mechanisms occurred during RF life-tests by means of 2D ATLAS-SILVACO simulations. Finally, the paper demonstrates that N-LDMOS degradation is linked to hot carriers generated interface states (traps) and trapped electrons, which results in a build up of negative charge at Si/SiO2 interface. More interface states are created at low temperature due to a located maximum impact ionization rate at the gate edge.

Electrical parameters degradation of power RF LDMOS device after accelerated ageing tests

This paper reports novel methods for accelerated ageing tests, with comparative reliability between them for stresses applied on power RF LDMOS: Thermal Shock Tests (TST), Thermal Cycling Tests (TCT), High Voltage Drain (HVD) and coupling thermal and electrical effects under various conditions. The investigation findings obtained after various ageing tests show the degradation and the devices performance shifts for most important electric parameters such as transconductance (Gm), on-state resistance (R ds_on ), feedback capacitance (C rss ) and gate-drain capacitance (C gd ). This means that the tracking of these parameters enables to consider the hot carrier injection as the dominant degradation phenomenon. However, this is explained by excitation and trapping of electrons in the oxide-silicon interface at the drain side. A physical simulation software (2D, Silvaco-Atlas) has been used to locate and confirm degradation phenomena.

Study of hot-carrier effects on power RF LDMOS device reliability

Abstract This paper reports comparative reliability of the hot carrier induced electrical performance degradation in power RF LDMOS transistors after RF life-tests and novel methods for accelerated ageing tests under various conditions (electrical and/or thermal stress): thermal shock tests (TST, air–air test) and thermal cycling tests (TCT, air–air test) under various conditions (with and without DC bias, TST cold and hot, different channel current I DS and different extremes temperatures Δ T values). It is important to understand the effects of the reliability degradation mechanisms on the S -parameters and in turn on static and dynamic parameters. The analysis of the experimental results is presented and the physical processes responsible for the observed degradation at different stress conditions are studied by means of 2D ATLAS-SILVACO simulations. The RF performance degradation of hot-carrier effects power RF LDMOS transistors can be explained by the transconductance and miller capacitance shifts, which are resulted from the interface state generation and trapped electrons, thereafter results in a build up of negative charge at Si/SiO 2 interface.

Characterization and modelling of power RF LDMOS transistor including self-heating effects

In this paper, we propose a new electro-thermal model of power RF LDMOS transistor implemented in Agilents ADS, using symbolic defined device (SDD). The proposed model takes into account the thermal effects and influence of temperature on the I-V characteristics, by providing three thermal capacitances and three thermal resistances, which represent the heat flow from the chip to the ambient air (thermal network). It allows us to study temperature dependent shifts for some macroscopic parameters such as the threshold voltage (V/sub t/), the transconductance (g/sub m/), the conductance (g/sub d/) and the on-state resistance (R/sub ds-on/).

Characterization of ESD stress effects on SiC MOSFETs using photon emission spectral signatures

This article presents a robustness study of SiC power MOSFETs to Electrostatic Discharge (ESD), by photon emission (PE) and spectral PE techniques (SPE). Investigations in different polarization modes are performed in photoemission PE, and a linear dependence in gate voltage has been identified. A decrease in the intensity of the ESD degraded device emissions has been noticed. A SPE system has been developed, and PE spectrum has been extracted for both fresh and degraded devices. SPE analyses are reported and correlated with electrical analyses to localize and identify the failure. The ESD degradation is seems to be related to a pn junction degradation. C-V analyses are conducted to prove this hypothesis.

Comparative analysis of RF LDMOS capacitance reliability under accelerated ageing tests

This paper presents the results of comparative reliability study of C–V characteristics through three accelerated ageing tests for stress applied to an RF LDMOS: Thermal shock tests (TST, air–air test), thermal cycling tests (TCT, air–air test) and high temperature storage life (HTSL). The two first tests are carried out with a drain current flowing through the device during stress. The investigation findings of electrical parameter degradations after various ageing tests are discussed. Feedback capacitance (Crs) is reduced by 16% and gate–drain capacitance (Cgd) by 42%. This means that the tracking of these parameters enables to consider the hot carrier injection as the dominant degradation phenomenon. A physical simulation software has been used to confirm qualitatively degradation phenomena.

A reliable guideline to maximize the detection and analysis of deep level defects: Comparison between DLTS analysis techniques

In this paper, we present reliable guidelines allowing to maximize the detection and analysis of deep defects in semiconductors by introducing a new method of analysis that we named Modified Levenberg-Marquardt Deep-Level Transient Spectroscopy (MLM-DLTS) based on the Levenberg-Marquardt algorithm that we modified deliberately and associated with two other high-resolution techniques, i.e. the Matrix Pencil algorithm and modified Pronys method. The performances of the method were first assessed with a procedure of simulation by generating multi-exponential capacitance transients with a changing signal-to-noise ratio. These different tests have demonstrated to what extent such a method of analysis is more efficient than classic correlation methods based on DLTS spectra and than three high-resolution methods already existing in the literature. Finally, when the signal-to-noise ratio is low, and in the aim of getting precise results, a few smoothing algorithms were tested. Our findings evidence how the smoothing quality can be controlled under certain conditions while avoiding both the distortions in the shape of the capacitance transients and the DLTS spectra.