Naeem Abbasi

Formal Reasoning about Expectation Properties for Continuous Random Variables

Expectation (average) properties of continuous random variables are widely used to judge performance characteristics in engineering and physical sciences. This paper presents an infrastructure that can be used to formally reason about expectation properties of most of the continuous random variables in a theorem prover. Starting from the relatively complex higher-order-logic definition of expectation, based on Lebesgue integration, we formally verify key expectation properties that allow us to reason about expectation of a continuous random variable in terms of simple arithmetic operations. In order to illustrate the practical effectiveness and utilization of our approach, we also present the formal verification of expectation properties of the commonly used continuous random variables: Uniform, Triangular and Exponential.

Formal Reliability Analysis Using Theorem Proving

Reliability analysis has become a tool of fundamental importance to virtually all electrical and computer engineers because of the extensive usage of hardware systems in safety and mission critical domains, such as medicine, military, and transportation. Due to the strong relationship between reliability theory and probabilistic notions, computer simulation techniques have been traditionally used to perform reliability analysis. However, simulation provides less accurate results and cannot handle large-scale systems due to its enormous CPU time requirements. To ensure accurate and complete reliability analysis and thus more reliable hardware designs, we propose to conduct a formal reliability analysis of systems within the sound core of a higher order logic theorem prover (HOL). In this paper, we present the higher order logic formalization of some fundamental reliability theory concepts, which can be built upon to precisely analyze the reliability of various engineering systems. The proposed approach and formalization is then utilized to analyze the repairability conditions for a reconfigurable memory array in the presence of stuck-at and coupling faults.

Formal Probabilistic Analysis of Stuck-at Faults in Reconfigurable Memory Arrays

Reconfigurable memory arrays with spare rows and columns are quite frequently used as reliable data storage components in present age System-on-Chips (SoCs). The spare memory rows and columns can be utilized to automatically replace rows or columns that are found to contain a cell fault after fabrication. One of the biggest SoC design challenges is to estimate, prior to the actual fabrication process, the right number of these spare rows and spare columns for meeting the reliability specifications. Traditionally, computer simulation techniques are used to perform probabilistic analysis of reconfigurable memory arrays but they provide inaccurate results. To ensure accurate analysis and thus more reliable SoC designs, we propose, in this paper, a probabilistic theorem proving approach in the domain of reconfigurable memory array analysis. We present a higher-order-logic stuck-at fault model for reconfigurable memory arrays, based on which, we illustrate the formal verification of some key statistical properties related to the number of stuck-at faults and the repairability condition.

On the simulation performance of contemporary AMS hardware description languages

Mixed-Signal extensions to VHDL, Verilog, and SystemC languages have been developed in order to provide a unifying environment for the modeling and verification of Analog and Mixed Signal (AMS) designs at different levels of abstraction. In this paper, we model the behavior of a set of benchmark designs in VHDL-AMS, Verilog-AMS and SystemC-AMS and compare the simulation performance with HSPICE. The various experimental results observed for the benchmark circuits show the superiority of VHDL-AMS and Verilog-AMS against SystemC-AMS and HSPICE in terms of simulation runtimes at lower level of abstraction.

An approach for lifetime reliability analysis using theorem proving

Recently proposed formal reliability analysis techniques have overcome the inaccuracies of traditional simulation based techniques but can only handle problems involving discrete random variables. In this paper, we extend the capabilities of existing theorem proving based reliability analysis by formalizing several important statistical properties of continuous random variables like the second moment and the variance. We also formalize commonly used concepts about the reliability theory such as survival, hazard, cumulative hazard and fractile functions. With these extensions, it is now possible to formally reason about important measures of reliability (the probabilities of failure, the failure risks and the mean-time-to failure) associated with the life of a system that operates in an uncertain and harsh environment and is usually continuous in nature. We illustrate the modeling and verification process with the help of examples involving the reliability analysis of essential electronic and electrical system components.

AOP-based high-level power estimation in SystemC

The paper presents a novel high-level power modeling and estimation framework. The approach is based on a synergic integration of aspect-oriented programming(AOP) and SystemC. Macro module modeling and power estimation are harnessed. A case study demonstrates the effectiveness of the proposed method.

Verification of analog and mixed signal designs using online monitoring

Analog and mixed signal (AMS) circuits play an important role in todays System on Chip design. They pose, however, many challenges in the verification of the overall system due to their complex behavior. Among many developed verification techniques, runtime verification has been shown to be effective by experimenting finite executions instead of going through the whole state space. In this paper, we present a methodology for the specification and verification of AMS designs using online monitoring at runtime based on the notion of System of Recurrence Equations (SREs). We implement the proposed methodology in a C language based tool, called C-SRE, and utilize it to verify several properties of a PLL design. We compare our proposed online monitoring techniques with the offline approach. Finally, we apply the proposed methodology to monitor the jitter noise associated with a voltage controlled oscillator.

Formal lifetime reliability analysis using continuous random variables

Reliability has always been an important concern in the design of engineering systems. Recently proposed formal reliability analysis techniques have been able to overcome the accuracy limitations of traditional simulation based techniques but can only handle problems involving discrete random variables. In this paper, we extend the capabilities of existing theorem proving based reliability analysis by formalizing several important statistical properties of continuous random variables, for example, the second moment and the variance. We also formalize commonly used reliability theory concepts of survival function and hazard rate. With these extensions, it is now possible to formally reason about important reliability measures associated with the life of a system, for example, the probability of failure and the mean-time-to-failure of the system operating in an uncertain and harsh environment, which is usually continuous in nature. We illustrate the modeling and verification process with the help of an example involving the reliability analysis of electronic system components.

Formal Analysis of Soft Errors using Theorem Proving.

Modeling and analysis of soft errors in electronic circuits has traditionally been done using computer simulations. Computer simulations cannot guarantee correctness of analysis because they utilize approximate real number representations and pseudo random numbers in the analysis and thus are not well suited for analyzing safety-critical applications. In this paper, we present a higher-order logic theorem proving based method for modeling and analysis of soft errors in electronic circuits. Our developed infrastructure includes formalized continuous random variable pairs, their Cumulative Distribution Function (CDF) properties and independent standard uniform and Gaussian random variables. We illustrate the usefulness of our approach by modeling and analyzing soft errors in commonly used dynamic random access memory sense amplifier circuits.

System-level power estimation using SystemC and aspect-oriented programming

Rapid system modelling and early evaluation of design characterisation are central to design space exploration. SystemC is used widely for system-level modelling, but it lacks the semantics to capture power consumption. The article presents a novel high-level power estimation methodology based on SystemC and aspect-oriented programming (AOP). Using a composite pattern, our methodology is applicable to the power estimation of a complex system. The proposed strategies support macro-models with multiple features. The experimental results are illustrated with case studies.