Gianfranco Gerosa

A 2.2 W, 80 MHz superscalar RISC microprocessor

A 28 mW/MHz at 80 MHz structured-custom RISC microprocessor design is described. This 32-b implementation of the PowerPC architecture is fabricated in a 3.3 V, 0.5 /spl mu/m, 4-level metal CMOS technology, resulting in 1.6 million transistors in a 7.4 mm by 11.5 mm chip size. Dual 8-kilobyte instruction and data caches coupled to a high performance 32/64-b system bus and separate execution units (float, integer, loadstore, and system units) result in peak instruction rates of three instructions per clock cycle. Low-power design techniques are used throughout the entire design, including dynamically powered down execution units. Typical power dissipation is kept under 2.2 W at 80 MHz. Three distinct levels of software-programmable, static, low-power operation-for system power management are offered, resulting in standby power dissipation from 2 mW to 350 mW. CPU to bus clock ratios of 1/spl times/, 2/spl times/, 3/spl times/, and 4/spl times/ are implemented to allow control of system power while maintaining processor performance. As a result, workstation level performance is packed into a low-power, low-cost design ideal for notebooks and desktop computers. >

Thermal management system for high performance PowerPC/sup TM/ microprocessors

Thermal management is an important design issue in high-performance, low-power portable computers. If the computer system is designed for worst-case processor power dissipation and environmental operating conditions, it carries an area and cost penalty for the system designer. The next-generation PowerPC/sup TM/ microprocessor includes a thermal assist unit (TAU) comprised of an on-chip thermal sensor and associated logic. The TAU monitors the junction temperature of the processor and dynamically adjusts processor operation to provide maximum performance under changing environmental conditions. The TAU is used in conjunction with other low-power features such as dynamic power management, instruction cache throttling and static low-power modes to provide comprehensive power and thermal management. This paper describes the implementation of the TAU and presents its characterization and operating data from first silicon.

A wide-bandwidth low-voltage PLL for PowerPC microprocessors

A 3.3 V Phase-Locked-Loop (PLL) clock synthesizer implemented in 0.5 /spl mu/m CMOS technology is described. The PLL supports internal to external clock frequency ratios of 1, 1.5, 2, 3, and 4 as well as numerous static power down modes for PowerPC microprocessors. The CPU clock lock range spans from 6 to 175 MHz. Lock times below 15 /spl mu/s, PLL power dissipation below 10 mW as well as phase error and jitter below /spl plusmn/100 ps have been measured. The total area of the PLL is 0.52 mm/sup 2/. >

PowerPC 603, a microprocessor for portable computers

The PowerPC 603 incorporates a variety of features to reduce power dissipation: dynamic idle-time shutdown of separate execution units, low-power cache design, and power considerations for standard cells, data-path elements, and clocking. System-level features include three software-programmable static power management modes and a hardware-programmable phase-lock loop. Operating at 80 MHz, the 603 typically dissipates 2.2 W, while achieving an estimated 75 Specint92 and 85 Specfp92.<<ETX>>

The PowerPC 603 microprocessor: a low-power design for portable applications

The PowerPC 603 microprocessor is a low-power implementation of the PowerPC architecture. The superscalar organization includes dynamic localized shutdown of execution units to reduce normal-mode power consumption. Three levels of static low-power operation are software programmable for system power management. The 603 PLL (phase lock loop) is capable of generating an internal processor clock at 1/spl times/, 2/spl times/, 3/spl times/ or 4/spl times/ the system clock speed to allow control of system power while maintaining processor performance. Various design features optimize the 603 for both power and performance, creating an ideal microprocessor solution for portable applications.<<ETX>>

A scalable resistor-less PLL design for PowerPC/sup TM/ microprocessors

A new resistor-less phase locked loop implemented in a 2.5 V, 0.35 /spl mu/m, CMOS technology is described. The design supports 13 different clock multiplier settings and uses a current-controlled-oscillator along with switched current sources to adjust the clock phase. Practical issues concerning system design and PLL stability parameters are also discussed. Simulation and characterization results show the response of the PLL to power supply and input clock modulation.