Mike Alexander

Thermal management system for high performance PowerPC/sup TM/ microprocessors

Thermal management is an important design issue in high-performance, low-power portable computers. If the computer system is designed for worst-case processor power dissipation and environmental operating conditions, it carries an area and cost penalty for the system designer. The next-generation PowerPC/sup TM/ microprocessor includes a thermal assist unit (TAU) comprised of an on-chip thermal sensor and associated logic. The TAU monitors the junction temperature of the processor and dynamically adjusts processor operation to provide maximum performance under changing environmental conditions. The TAU is used in conjunction with other low-power features such as dynamic power management, instruction cache throttling and static low-power modes to provide comprehensive power and thermal management. This paper describes the implementation of the TAU and presents its characterization and operating data from first silicon.

DFT advances in the Motorola's MPC7400, a PowerPC/sup TM/ G4 microprocessor

Several advances have been made in the design for testability of the MPC7400, the first fourth generation PowerPC microprocessor. The memory array built-in self-test algorithms now support detecting write-recovery defects and more comprehensive diagnostics. Delay defects can be tested with scan patterns with the phased locked loop providing the at-speed launch-capture events. Several methodology and modeling improvements increased LSSD stuck-at fault test coverage. Design for manufacturability enhancements provide better tracking of initial silicon and fuse-based memory repair capabilities for improved yield and time-to-market.

The PowerPC 603 microprocessor: a high performance, low power, superscalar RISC microprocessor

The PowerPC 603 microprocessor is the second member of the PowerPC microprocessor family. The 603 is a superscalar implementation featuring low power operation of less than 3 watts while maintaining high performance of 75 SPECint92 (estimated) at 80 MHz. The 7.4 mm by 11.5 mm design is implemented in 0.5 /spl mu/m, four-level metal CMOS technology. The 603 features dual 8-kByte instruction and data caches and a 32/64-bit system bus. Peak instruction rates of 3 instructions per clock cycle give outstanding performance to notebook and portable applications.<<ETX>>

A 250 MHz 5 W RISC microprocessor with on-chip L2 cache controller

This superscalar microprocessor is a 32b implementation of the PowerPC Architecture(TM) specification based on a micro-architecture designed for high performance and low power. Two instructions per cycle can be dispatched in this superscalar design. The processor includes dual 32kB 8-way instruction and data caches, a floating-point unit, two integer units, a branch unit, a load/store unit, and a system unit. An L2 tag and cache controller with a dedicated L2 bus interface are added to provide a low-cost L2 cache solution using commodity SRAMs for the data.

A scalable resistor-less PLL design for PowerPC/sup TM/ microprocessors

A new resistor-less phase locked loop implemented in a 2.5 V, 0.35 /spl mu/m, CMOS technology is described. The design supports 13 different clock multiplier settings and uses a current-controlled-oscillator along with switched current sources to adjust the clock phase. Practical issues concerning system design and PLL stability parameters are also discussed. Simulation and characterization results show the response of the PLL to power supply and input clock modulation.

The PowerPC 603e microprocessor: an enhanced, low-power, superscalar microprocessor

The PowerPC 603e microprocessor is a high performance, low cost, low power microprocessor designed for use in portable computers. The 603e is an enhanced version of the PowerPC 603 microprocessor and extends the performance range of the PowerPC microprocessor family of portable products. The enhancements include increasing the frequency to 100 MHZ doubling the on-chip instruction and data caches to 16 Kbytes each, increasing the cache associativity to 4-way set-associative, adding an extra integer unit, and increasing the throughput of stores and misaligned accesses. Three new bus modes are added to allow for more flexibility in system design. The estimated performance of the 603e at 100 MHz is 120 SPECint92 and 105 SPECfp92. The 603e is fabricated in the same 3.3 volt, 0.5 micron, four-level metal technology as the 603 and contains 2.6 million transistors. The die size is 98 mm/sup 2/. The typical power consumption of the 603e at 100 MHz is 3 watts. Like the 603, the 603e provides three software controllable power-down modes to further extend power saving capability.

A 66-MHz configurable secondary cache controller with primary cache copyback support

The authors describe a 66-MHz secondary cache controller which supports a primary cache operating in copyback mode. The device integrates a 278-kb direct-mapped cache tag array plus control logic to provide full multiprocessing capability and is configurable to support cache sizes from 256 kbytes to 1 Mbyte. Implemented in a 0.8- mu m twin-well double-poly triple-metal CMOS process, the device uses a high-resistivity poly load memory cell to achieve high density.<<ETX>>