Gianluca Fiori
University of Pisa
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Publication
Featured researches published by Gianluca Fiori.
Nature Nanotechnology | 2014
Gianluca Fiori; Francesco Bonaccorso; Giuseppe Iannaccone; Tomas Palacios; Daniel Neumaier; Alan Seabaugh; Sanjay K. Banerjee; Luigi Colombo
The compelling demand for higher performance and lower power consumption in electronic systems is the main driving force of the electronics industrys quest for devices and/or architectures based on new materials. Here, we provide a review of electronic devices based on two-dimensional materials, outlining their potential as a technological option beyond scaled complementary metal-oxide-semiconductor switches. We focus on the performance limits and advantages of these materials and associated technologies, when exploited for both digital and analog applications, focusing on the main figures of merit needed to meet industry requirements. We also discuss the use of two-dimensional materials as an enabling factor for flexible electronics and provide our perspectives on future developments.
IEEE Electron Device Letters | 2007
Gianluca Fiori; Giuseppe Iannaccone
We present an atomistic 3-D simulation of graphene nanoribbon field-effect transistors (GNR-FETs), based on the self consistent solution of the 3-D Poisson and Schrodinger equations with open boundary conditions within the nonequilibrium Greens function formalism and a tight-binding Hamiltonian. With respect to carbon nanotube FETs, GNR-FETs exhibit comparable performance, reduced sensitivity to the variability of channel chirality, and similar leakage problems due to band-to-band tunneling. Acceptable transistor performance requires prohibitive effective nanoribbon width of 1-2 nm and atomistic precision that could in principle be obtained with periodic etch patterns or stress patterns.
IEEE Electron Device Letters | 2009
Gianluca Fiori; Giuseppe Iannaccone
In this letter, we propose the bilayer graphene tunnel field-effect transistor (TFET) as a device suitable for fabrication and circuit integration with present-day technology. It provides high I on/I off ratio at ultralow supply voltage, without the limitations in terms of prohibitive lithography and patterning requirements for circuit integration of graphene nanoribbons. Our investigation is based on the solution of the coupled Poisson and Schrodinger equations in three dimensions, within the non-equilibrium Greens function formalism on a tight binding Hamiltonian. We show that the small achievable gap of only few hundreds of millielectronvolts is still enough for promising TFET operation, providing a large I on/I off ratio in excess of 103 even for a supply voltage of only 0.1 V. A key to this performance is the low quantum capacitance of bilayer graphene, which permits to obtain an extremely small subthreshold swing S smaller than 20 mV/dec at room temperature.
Applied Physics Letters | 2011
Samantha Bruzzone; Gianluca Fiori
We present an ab-initio study of electron mobility and electron-phonon coupling in chemically modified graphene, considering fluorinated and hydrogenated graphene at different percentage coverage. Hexagonal boron carbon nitrogen is also investigated due the increased interest shown by the research community towards this material. In particular, the deformation potentials are computed by means of density functional theory, while the carrier mobility is obtained according to the Takagi model (S. Takagi, A. Toriumi, and H. Tango, IEEE Trans. Electron Devices 41, 2363 (1994)). We will show that graphene with a reduced degree of hydrogenation can compete, in terms of mobility, with silicon technology.
IEEE Transactions on Electron Devices | 2008
Youngki Yoon; Gianluca Fiori; Seokmin Hong; Giuseppe Iannaccone; Jing Guo
We present an atomistic 3-D simulation study of the performance of graphene-nanoribbon (GNR) Schottky-barrier field-effect transistors (SBFETs) and transistors with doped reservoirs (MOSFETs) by means of the self-consistent solution of the Poisson and Schrodinger equations within the nonequilibrium Greens function (NEGF) formalism. Ideal MOSFETs show slightly better electrical performance for both digital and terahertz applications. The impact of nonidealities on device performance has been investigated, taking into account the presence of single vacancy, edge roughness, and ionized impurities along the channel. In general, MOSFETs show more robust characteristics than SBFETs. Edge roughness and single-vacancy defect largely affect the performance of both device types.
Nano Letters | 2012
B. N. Szafranek; Gianluca Fiori; Daniel Schall; Daniel Neumaier; H. Kurz
The emergence of graphene with its unique electrical properties has triggered hopes in the electronic devices community regarding its exploitation as a channel material in field effect transistors. Graphene is especially promising for devices working at frequencies in the 100 GHz range. So far, graphene field effect transistors (GFETs) have shown cutoff frequencies up to 300 GHz, while exhibiting poor voltage gains, another important figure of merit for analog high frequency applications. In the present work, we show that the voltage gain of GFETs can be improved significantly by using bilayer graphene, where a band gap is introduced through a vertical electric displacement field. At a displacement field of -1.7 V/nm the bilayer GFETs exhibit an intrinsic voltage gain up to 35, a factor of 6 higher than the voltage gain in corresponding monolayer GFETs. The transconductance, which limits the cutoff frequency of a transistor, is not degraded by the displacement field and is similar in both monolayer and bilayer GFETs. Using numerical simulations based on an atomistic p(z) tight-binding Hamiltonian we demonstrate that this approach can be extended to sub-100 nm gate lengths.
ACS Nano | 2012
Gianluca Fiori; Alessandro Betti; Samantha Bruzzone; Giuseppe Iannaccone
We propose that lateral heterostructures of single-atomic-layer graphene and hexagonal boron-carbon-nitrogen (hBCN) domains, can represent a powerful platform for the fabrication and the technological exploration of real two-dimensional field-effect transistors. Indeed, hBCN domains have an energy bandgap between 1 and 5 eV, and are lattice-matched with graphene; therefore they can be used in the channel of a FET to effectively inhibit charge transport when the transistor needs to be switched off. We show through ab initio and atomistic simulations that a FET with a graphene-hBCN-graphene heterostructure in the channel can exceed the requirements of the International Technology Roadmap for Semiconductors for logic transistors at the 10 and 7 nm technology nodes. Considering the main figures of merit for digital electronics, a FET with gate length of 7 nm at a supply voltage of 0.6 V exhibits I(on)/I(off) ratio larger than 10(4), intrinsic delay time of about 0.1 ps, and a power-delay-product close to 0.1 nJ/m. More complex graphene-hBCN heterostructures can allow the realization of different multifunctional devices, translating on a truly two-dimensional structure some of the device principles proposed during the first wave of nanoelectronics based on III-V heterostructures, as for example the resonant tunneling FET.
IEEE Electron Device Letters | 2009
Gianluca Fiori; Giuseppe Iannaccone
We explore the device potential of a tunable-gap bilayer graphene (BG) FET exploiting the possibility of opening a bandgap in BG by applying a vertical electric field via independent gate operation. We evaluate device behavior using atomistic simulations based on the self-consistent solution of the Poisson and Schrodinger equations within the nonequilibrium Greens function formalism. We show that the concept works, but the bandgap opening is not strong enough to suppress band-to-band tunneling in order to obtain a sufficiently large Ion/Ioff ratio for CMOS device operation.
IEEE Transactions on Electron Devices | 2006
Gianluca Fiori; Giuseppe Iannaccone; Gerhard Klimeck
This paper simulates the expected device performance and scaling perspectives of carbon nanotube (CNT) field-effect transistors with doped source and drain extensions. The simulations are based on the self-consistent solution of the three-dimensional Poisson-Schroumldinger equation with open boundary conditions, within the nonequilibrium Greens function formalism, where arbitrary gate geometry and device architecture can be considered. The investigation of short channel effects for different gate configurations and geometry parameters shows that double-gate devices offer quasi-ideal subthreshold slope and drain-induced barrier lowering without extremely thin gate dielectrics. Exploration of devices with parallel CNTs shows that on currents per unit width can be significantly larger than the silicon counterpart, while high-frequency performance is very promising
Proceedings of the IEEE | 2013
Gianluca Fiori; Giuseppe Iannaccone
The quest for developing graphene-based nanoelectronics puts new requirements on the science and technology of device modeling. It also heightens the role of device modeling in the exploration and in the early assessment of technology options. Graphene-based nanoelectronics is the first form of molecular electronics to reach real prominence, and therefore the role of single atoms and of chemical properties acquires more relevance than in the case of bulk semiconductors. In addition, the promising perspectives offered by band engineering of graphene through chemical modifications increase the role of quantum chemistry methods in the assessment of material properties. In this paper, we review the multiphysics multiscale (MS) approaches required to model graphene-based materials and devices, presenting a comprehensive overview of the main physical models providing a quantitative understanding of the operation of nanoscale transistors. We especially focus on the ongoing efforts to consistently connect simulations at different levels of physical abstraction in order to evaluate materials, device, and circuit properties. We discuss various attempts to induce a gap in graphene-based materials and their impact on the operation of different transistor structures. Finally, we compare candidate devices in terms of integrated circuit performance and robustness to process variability.