Gianluigi De Geronimo

Prospects for charge sensitive amplifiers in scaled CMOS

Due to its low cost and flexibility for custom design, monolithic CMOS technology is being increasingly employed in charge preamplifiers across a broad range of applications, including both scientific research and commercial products. The associated detectors have capacitances ranging from a few tens of fF to several hundred pF. Applications call for pulse shaping from tens of ns to tens of μs, and constrain the available power per channel from tens of μW to tens of mW. At the same time a new technology generation, with changed device parameters, appears every 2 years or so. The optimum design of the front-end circuitry is examined taking into account submicron device characteristics, weak inversion operation, the reset system, and power supply scaling. Experimental results from recent prototypes will be presented. We will also discuss the evolution of preamplifier topologies and anticipated performance limits as CMOS technology scales down to the 0.1 μm/1.0 V generation in 2006.

Analog CMOS peak detect and hold circuits. Part 1. Analysis of the classical configuration

Peak detectors (peak-detect-and-hold circuits, PDHs) are a key element in nuclear electronics signal processing and have been incorporated as a fully integrated block in several front-end readout chips. In CMOS designs, the PDH uses an MOS current source as the rectifying element inside the feedback loop of a high-gain amplifier. However, the nonidealities in the amplifier and feedback elements significantly limit its accuracy and stability. This paper reports on the limits of the classical CMOS PDH. Static errors due to offset, finite gain, and commonmode rejection, dynamic errors due to parasitic capacitive coupling and slew rate, and loop stability are analyzed. Expressions for each error source and consequent design tradeoffs between accuracy, speed, and dynamic range, and driving capability are derived. In a related article (Part 2), a two-phase PDH configuration, which overcomes the major limits of the classical approach is presented. r 2002 Elsevier Science B.V. All rights reserved.

Analog CMOS peak detect and hold circuits. Part 2. The two-phase offset-free and derandomizing configuration ☆

An analog CMOS peak detect and hold (PDH) circuit, which combines high speed and accuracy, rail-to-rail sensing and driving, low power, and buffering is presented. It is based on a configuration that cancels the major error sources of the classical CMOS PDH, including offset and common mode gain, by re-using the same amplifier for tracking, peak sensing, and output buffering. By virtue of its high absolute accuracy, two or more PDHs can be used in parallel to serve as a data-driven analog memory for derandomization. The first experimental results on the new peak detector and derandomizer (PDD) circuit, fabricated in 0.35mm CMOS technology, include a 0.2% absolute accuracy for pulses with 500 ns peaking time, 2.7 V linear input range, 3.3 mW power dissipation, 250 mV/s droop rate, and negligible dead time. The use of such a high performance analog PDD can greatly relax the requirements on the digitization in multi-channel systems. r 2002 Elsevier Science B.V. All rights reserved.

A CMOS DETECTOR LEAKAGE CURRENT SELF-ADAPTABLE CONTINUOUS RESET SYSTEM : THEORETICAL ANALYSIS

Abstract A continuous reset system for the discharge of the feedback capacitance of integrated charge preamplifiers is presented. The system, based on the use of a FET operating in the saturation region, is self-adaptable with respect to a wide range of detector leakage currents. A circuit which provides compensation of the signal from the charge amplifier is also proposed. The noise analysis, which takes into account both the stationary and non-stationary noise contributions and the effect of the rate, shows that the system, when carefully designed, can offer good signal/noise performance for applications in γ-ray and high-energy X-ray spectroscopy. Practical layout considerations are also made.

Transmission-mode diamond white-beam position monitor at NSLS

Two transmission-mode diamond X-ray beam position monitors installed at National Synchrotron Light Source (NSLS) beamline X25 are described. Each diamond beam position monitor is constructed around two horizontally tiled electronic-grade (p.p.b. nitrogen impurity) single-crystal (001) CVD synthetic diamonds. The position, angle and flux of the white X-ray beam can be monitored in real time with a position resolution of 500 nm in the horizontal direction and 100 nm in the vertical direction for a 3 mm × 1 mm beam. The first diamond beam position monitor has been in operation in the white beam for more than one year without any observable degradation in performance. The installation of a second, more compact, diamond beam position monitor followed about six months later, adding the ability to measure the angular trajectory of the photon beam.

ASIC for SDD-Based X-Ray Spectrometers

We present an application-specific integrated circuit (ASIC) for high-resolution x-ray spectrometers (XRS). The ASIC reads out signals from pixelated silicon drift detectors (SDDs). The pixel does not have an integrated field effect transistor (FET); rather, readout is accomplished by wire-bonding the anodes to the inputs of the ASIC. The ASIC dissipates 32 mW, and offers 16 channels of low-noise charge amplification, high-order shaping with baseline stabilization, discrimination, a novel pile-up rejector, and peak detection with an analog memory. The readout is sparse and based on custom low-power tristatable low-voltage differential signaling (LPT-LVDS). A unit of 64 SDD pixels, read out by four ASICs, covers an area of 12.8 cm2 and dissipates with the sensor biased about 15 mW/cm2. As a tile-based system, the 64-pixel units cover a large detection area. Our preliminary measurements at -44°C show a FWHM of 145 eV at the 5.9 keV peak of a 55Fe source, and less than 80 eV on a test-pulse line at 200 eV.

Cold Electronics for Giant Liquid Argon Time Projection Chambers

The choice between cold and warm electronics (inside or outside the cryostat) in very large LAr TPCs (>5-10 ktons) is not an electronics issue, but it is rather a major cryostat design issue. This is because the location of the signal processing electronics has a direct and far reaching effect on the cryostat design, an indirect effect on the TPC electrode design (sense wire spacing, wire length and drift distance), and a significant effect on the TPC performance. All these factors weigh so overwhelmingly in favor of the cold electronics that it remains an optimal solution for very large TPCs. In this paper signal and noise considerations are summarized, the concept of the readout chain is described, and the guidelines for design of CMOS circuits for operation in liquid argon (at ~89 K) are discussed.

Advanced-readout ASICs for multielement CdZnTe detectors

A generation of high performance front-end and read-out ASICs customized for highly segmented CdZnTe sensors is presented. The ASICs, developed in a multi-year effort at Brookhaven National Laboratory, are targeted to a wide range of applications including medical, safeguards/security, industrial, research, and spectroscopy. The front-end multichannel ASICs provide high accuracy low noise preamplification and filtering of signals, with ver-sions for small and large area CdZnTe elements. They implement a high order unipolar or bipolar shaper, an innovative low noise continuous reset system with self-adapting capability to the wide range of detector leakage currents, a new system for stabilizing the output baseline and high output driving capability. The general-purpose versions include pro-grammable gain and peaking time. The read-out multichannel ASICs provide fully data driven high accuracy amplitude and time measurements, multiplexing and time domain derandomization of the shaped pulses. They implement a fast arbitration scheme and an array of innovative two-phase offset-free rail-to-rail analog peak detectors for buffering and absorption of input rate fluctuations, thus greatly relaxing the rate requirement on the external ADC. Pulse amplitude, hit timing, pulse risetime, and channel address per processed pulse are available at the output in correspondence of an exter-nal readout request. Prototype chips have been fabricated in 0.5 and 0.35 μm CMOS and tested. Design concepts and experimental results are discussed.

AXTAR: Mission Design Concept

The Advanced X-ray Timing Array (AXTAR) is a mission concept for X-ray timing of compact objects that combines very large collecting area, broadband spectral coverage, high time resolution, highly flexible scheduling, and an ability to respond promptly to time-critical targets of opportunity. It is optimized for submillisecond timing of bright Galactic X-ray sources in order to study phenomena at the natural time scales of neutron star surfaces and black hole event horizons, thus probing the physics of ultradense matter, strongly curved spacetimes, and intense magnetic fields. AXTARs main instrument, the Large Area Timing Array (LATA) is a collimated instrument with 2-50 keV coverage and over 3 square meters effective area. The LATA is made up of an array of supermodules that house 2-mm thick silicon pixel detectors. AXTAR will provide a significant improvement in effective area (a factor of 7 at 4 keV and a factor of 36 at 30 keV) over the RXTE PCA. AXTAR will also carry a sensitive Sky Monitor (SM) that acts as a trigger for pointed observations of X-ray transients in addition to providing high duty cycle monitoring of the X-ray sky. We review the science goals and technical concept for AXTAR and present results from a preliminary mission design study.

Pixelated transmission-mode diamond X-ray detector

Fabrication and testing of a prototype transmission-mode pixelated diamond X-ray detector (pitch size 60-100 µm), designed to simultaneously measure the flux, position and morphology of an X-ray beam in real time, are described. The pixel density is achieved by lithographically patterning vertical stripes on the front and horizontal stripes on the back of an electronic-grade chemical vapor deposition single-crystal diamond. The bias is rotated through the back horizontal stripes and the current is read out on the front vertical stripes at a rate of ∼ 1 kHz, which leads to an image sampling rate of ∼ 30 Hz. This novel signal readout scheme was tested at beamline X28C at the National Synchrotron Light Source (white beam, 5-15 keV) and at beamline G3 at the Cornell High Energy Synchrotron Source (monochromatic beam, 11.3 keV) with incident beam flux ranges from 1.8 × 10(-2) to 90 W mm(-2). Test results show that the novel detector provides precise beam position (positional noise within 1%) and morphology information (error within 2%), with an additional software-controlled single channel mode providing accurate flux measurement (fluctuation within 1%).