Gianni Signorini

Parameterized and DC-Compliant Small-Signal Macromodels of RF Circuit Blocks

This paper presents a new approach for the generation of reduced-order compact macromodels of analog circuit blocks (CBs) in highly integrated radio frequency and analog/mixed-signal design. The circuits under investigation are designed and assumed to operate at certain bias points, where they should perform as linear as possible. Therefore, they can be well approximated to first order by linearized transfer function models, assuming small-signal excitation around these operating points. This paper concentrates on a number of key aspects. First, a fully parameterized macromodeling flow is described, for the closed-form inclusion of external geometrical or design parameters in the macromodel responses. This aspect is important for fast optimization, design centering, and what-if analyses. Second, a parameterized DC correction strategy is presented, to guarantee that the DC response of the linearized macromodel matches to machine precision the true DC responses of the original CB. This aspect is fundamental when the macromodel is used in a system-level simulation deck that combines linearized and fully nonlinear models of other components. The main result of proposed approach is a SPICE-compatible reduced-order macromodel that can replace complex transistor-level CBs plus passive interconnect networks, thus enabling dramatic speedup in transient system-level analyses and signal integrity verifications.

Present and future of I/O-buffer behavioral macromodels

Modern Signal and Power Integrity (SI/PI) verification flows rely on accurate models for complex I/O-buffers that drive and receive electrical signals on high-speed channels. The sheer density of modern integrated circuits makes detailed transistor-level descriptions computationally cumbersome to the point where they become unusable for system-level simulations. Fortunately, transistor-level descriptions may be replaced with more compact representations that approximate the input/output buffers behavior with considerable accuracy while providing a simulation speedup of several orders of magnitude. Known as behavioral models, surrogate models or macromodels, these computationally efficient equivalents have become a de-facto industry standard in SI/ PI simulations. This paper presents an overview of the state-of-the-art in I/O-buffer behavioral modeling, introducing the main features of both standard and emerging solutions. Open issues and future research directions are also discussed.

Thermal Noise Compliant Synthesis of Linear Lumped Macromodels

This paper addresses the synthesis of equivalent circuits from black box state-space macromodels, as produced by model order reduction or rational curve fitting schemes. The emphasis is here on thermal noise compliance, intended as the guarantee that the produced netlists can be safely used in standard circuit solvers to perform thermal noise analysis, in addition to usual DC, AC, and transient simulations. Due to the fact that SNR is a key figure of merit in nearly all signal processing analog circuits, noise analysis is mandatory in design and verification of most analog and RF/millimeter-wave electronic applications. However, common macromodel synthesis approaches rely on components that do not (and cannot) have an associated thermal noise model, such as controlled sources or negative circuit elements. Therefore, macromodel-based noise analyses are generally not possible with currently available approaches. We propose a circuit realization derived from the classical resistance extraction synthesis, with suitable modifications for enhancing macromodel sparsity and efficiency. The resulting equivalent netlist, which is compatible with any standard circuit solver, is shown to produce exact noise characteristics, even if its elements are derived through a mathematical procedure, totally unrelated to the actual topology of the physical system under modeling. The procedure is validated by several examples.

Macromodeling of I/O Buffers via Compressed Tensor Representations and Rational Approximations

This paper addresses the generation of accurate and efficient macromodels of high-speed input/output buffers. The proposed modeling approach extends the state-of-the-art methods that are currently available, yielding to a modular and scalable tool for model generation. The modeling procedure applies to both single-ended and differential devices, possibly exhibiting a rich dynamical behavior due to large supply fluctuations or internal voltage regulators. The models are defined by the combination of static surfaces described via compact tensor approximations and linear dynamical state-space relations generated using a robust time-domain vector fitting algorithm. A simple and effective solution is adopted to account for the overclocking operation of output buffer models as well. The feasibility and strength of the proposed method are demonstrated using real devices and complex application test cases for signal and power integrity cosimulations.

Behavioral macromodeling of high-speed drivers via compressed tensor representations

This paper addresses the behavioral modeling of digital drivers for Signal and Power Integrity co-simulations. State-of-the-art two-piece model representations are combined with a compact description of the device static characteristics. The latter are considered as multivariate mappings that are functions of the device electrical variables, and of additional parameters defining process corners and device settings. Overall model complexity is reduced through a compressed tensor representation obtained via a high-order singular value decomposition. Several application examples demonstrate the feasibility and the advantages of the proposed approach.

Enhanced macromodels of high-speed low-power differential drivers

High-speed differential interfaces implementing specific solutions for low-power consumption and low-EMI disturbances are vastly used in mobile platforms. In these devices, the slew rate is suitably controlled, the communication scheme alternates data-bursts followed by power-saving states, the voltage swing and the common-mode level are reduced. To achieve these targets, a key role in voltage-mode output drivers is played by an internal voltage-regulator. The latter exhibits a rich dynamic behavior, with non-negligible effects on the transmitter outputs, that need to be carefully characterized. In this paper, a modeling strategy based on a few key enhancements of state-of-the-art solutions is presented, leading to compact and accurate models. The feasibility and strengths of the proposed approach are verified on a low-power high-speed voltage-mode driver.

Macromodel-based Signal and Power Integrity simulations of an LP-DDR2 interface in mSiP

Signal and Power Integrity (SI/PI) analyses assume a paramount importance to ensure a secure integration of high-speed communication interfaces in low-cost highly-integrated System-in-Package(s) (SiP) for mobile applications. In an iterative fashion, design and time-domain SI/PI verifications are alternated to assess and optimize system functionality. The resulting complexity of the analysis limits simulation coverage and requires extremely long runtimes (hours, days). In order to ensure post-silicon correlation, electrical macromodels of Package/PCB parasitics and high-speed I/Os can be generated and included in the testbenches to expedite simulations. Using as example an LP-DDR2 memory interface to support the operations of a mobile digital base-band processor, we have developed and applied a macromodelling flow to demonstrate simulation run-time speed-up factors (x1200+), and enable interface-level analyses to study the effects of Package/PCB parasitics on signals and PDNs, as well as the corresponding degradation in the timing budget.

Compact parameterized macromodels for signal and power integrity analysis of RF and mixed signal systems

Linear macromodeling techniques are well established for compact dynamical modeling of complex signal and power distribution networks. In this work, we extend applicability of such reduced-order behavioral models to small-signal descriptions of complex circuit blocks typically found in RF or Analog and Mixed/Signal designs. In addition, we include in the models the explicit dependence on one or more design parameters, such as temperature, bias or gain, thus obtaining a multivariate small-signal behavioral macromodeling approach. The main outcome is a major reduction in the runtime required for transient system-level verification, which can be performed directly by simulating the surrogate macromodels rather than full transistor-level circuits. We demonstrate this approach through an Operarional Amplifier circuit block of a commercial 3G transceiver design.