Igor Simone Stievano

Macromodel-based Signal and Power Integrity simulations of an LP-DDR2 interface in mSiP

Signal and Power Integrity (SI/PI) analyses assume a paramount importance to ensure a secure integration of high-speed communication interfaces in low-cost highly-integrated System-in-Package(s) (SiP) for mobile applications. In an iterative fashion, design and time-domain SI/PI verifications are alternated to assess and optimize system functionality. The resulting complexity of the analysis limits simulation coverage and requires extremely long runtimes (hours, days). In order to ensure post-silicon correlation, electrical macromodels of Package/PCB parasitics and high-speed I/Os can be generated and included in the testbenches to expedite simulations. Using as example an LP-DDR2 memory interface to support the operations of a mobile digital base-band processor, we have developed and applied a macromodelling flow to demonstrate simulation run-time speed-up factors (x1200+), and enable interface-level analyses to study the effects of Package/PCB parasitics on signals and PDNs, as well as the corresponding degradation in the timing budget.

Behavioral Modeling of Flash Memories

Over the past ten years, the interest in the development of accurate and efficient models of high-speed digital integrated circuits (ICs) has grown. The generation of IC models is of paramount importance for the simulation of many advanced electronic applications. IC models are used in system level simulation to predict the integrity of the signals flowing through the system interconnects and the switching noise generated by the current absorption of the circuits, that can interfere on the stable functioning of the entire system. In this scenario, the common modeling resource is based on the detailed description of the IC functional behavior obtained from the information on the internal structure of devices and on the their physical governing equations. These models, however, are seldom available since they disclose proprietary information of silicon vendors. In addition they turn out to be extremely inefficient to handle the complexity of recent devices and demand for the availability of simplified models. Owing to this, the most promising strategy is the generation of the so-called behavioral models or macromodels, that mimic the external behavior of a device and that can be obtained from external simulations or measurements. A typical example of devices that strongly demand for the availability of reliable behavioral models is represented by the class of digital memories, that are widely used in modern electronic equipments and that are often provided by external suppliers along with low-order or partial models only. The modeling of the power delivery network of ICs is addressed in (ICEM, 2001; Labussiere-Dorgan et al., 2008; Stievano et al., 2011b) and the modeling of I/O ports in (Stievano et al., 2004; Mutnury et. al., 2006; IBIS, 2008; Pulici et al., 2008; Cao and Zhang, 2009; Stievano et al., 2011a). In these contributions most of the efforts are made to define and improve the model structures and to provide general modeling guidelines for the computation of model parameters from both numerical simulations and real measurements. The aim of this chapter is to provide a unified modeling framework for the combined application of state-of-the-art techniques to the generation of behavioral models of digital ICs from numerical simulation and real measured data. All the results presented in this study are based on a 512Mb NOR Flash memory in 90 nm technology produced by Numonyx, which is representative of a wide class of memory chips.