Gilberto Curatola

Double-Gate finFETs as a CMOS Technology Downscaling Option: An RF Perspective

Based on careful physical description, the effect of gate-length downscaling on the RF performance of double-gate fin field-effect transistors (finFETs) has been analyzed. Downscaling is beneficial to the device RF performance although the losses due to series parasitics increase. The source/drain series resistance in finFET largely limits the device RF performance, and the losses due to the gate resistance increase with reducing gate length. Double-gate finFETs have the potential to reach the RF International Technology Roadmap for Semiconductor targets in the few decananometer regime, but meeting the specification for gate length in the order of 10 nm may require further improvements

Influence of Buffer Carbon Doping on Pulse and AC Behavior of Insulated-Gate Field-Plated Power AlGaN/GaN HEMTs

Pulse behavior of insulated-gate double-field-plate power AlGaN/GaN HEMTs with C-doped buffers showing small current-collapse effects and dynamic RDS,on increase can accurately be reproduced by numerical device simulations that assume the CN-CGa autocompensation model as carbon doping mechanism. Current-collapse effects much larger than experimentally observed are instead predicted by simulations if C doping is accounted by dominant acceptor states. This suggests that buffer growth conditions favoring CN-CGa autocompensation can allow for the fabrication of power AlGaN/GaN HEMTs with reduced current-collapse effects. The drain-source capacitance of these devices is found to be a sensitive function of the C doping model, suggesting that its monitoring can be adopted as a fast technique to assess buffer compensation properties.

Direct Solution of the Boltzmann Transport Equation and Poisson–SchrÖdinger Equation for Nanoscale MOSFETs

We propose an efficient and fast algorithm to solve the coupled Poisson-Schrodinger and Boltzmann transport equations (BTE) in two dimensions. The BTE is solved in the relaxation time approximation within each subband obtained from the direct solution of the Schrodinger equation. The proposed approach, considering a subband-based transport formalism, allows to fully explore the entire range from drift-diffusion to ballistic regime in nanoscale field-effect transistors. Quantum effects are also fully taken into account by the direct solution of the Schrodinger equation. The model is implemented in the NanoTCAD2D device simulator and used to study the device performance of a 25-nm channel-length MOSFET. The influence of scattering on the electron distribution function and on device characteristics is analyzed in detail.

Effective Bohm Quantum Potential for device simulators based on drift-diffusion and energy transport

In this paper we present a derivation of a very convenient approach to include quantum confinement effects in drift-diffusion or hydrodynamic device simulators, without explicitly solving the Schrodinger equation. With respect to similar methods recently proposed in the literature, the presented approach has a few advantages: it does not depend on the transport model (drift-diffusion or hydrodynamic); it can straightforwardly include Fermi-Dirac statistics; it provides an additional degree of freedom for calibration, which is particularly useful for considering non planar device structures; finally, it can be discretized in such a way to exhibit very stable convergence properties.

Gate-stack analysis for 45-nm CMOS devices from an RF perspective

Three gate stacks for the 45-nm node are analyzed from an RF perspective. The authors present an expression of the gate resistance valid for all three stacks, quantify the differences each stack has on several small-signal RF figures-of-merit and on the RF noise parameters, and demonstrate that devices with fully silicided gates will enable ultralow-power/low-noise RF applications, while the performance of transistors using multilayer gate stacks are limited by large contact resistance. Although offering better bandwidth and noise characteristics than the poly/silicide stack, the deposited metal stack will lose its advantage in devices requiring higher gate work functions than in planar bulk CMOS transistors.

Threshold voltage instabilities in D-mode GaN HEMTs for power switching applications

Threshold voltage instabilities observed in GaN HEMTs designed for power switching applications when submitted to either DC or pulsed testing are here presented and interpreted. Main results can be summarized as follows: i) two acceptor trap levels, characterized by two well distinct time constants, are present in the UID GaN channel and C-doped GaN buffer respectively and behave as electron and hole traps respectively; ii) the trapped charge is modulated by the high voltage biasing of the gate and drain terminals; iii) when empty, channel electron traps induce a negative threshold-voltage shift, while buffer hole traps induce a positive threshold-voltage shift; iv) when the device is pulsed from off- to on-state conditions, trap charge/discharge dynamics induces negative and positive threshold-voltage instabilities over distinct time scales.

GaN virtual prototyping: From traps modeling to system-level cascode optimization

The present paper focuses on the system-level optimization of GaN technology for high voltage applications. We will show that a key requirement for the future success of the GaN technology is the full system-optimization achieved by a simultaneous optimization of technology, packaging and applications. We will also show that Virtual Prototyping (VP) becomes, in GaN technology, a fundamental tool that allows not only to have a fundamental understanding of the device properties but more importantly it allows to strongly link device optimization, technology and system-level performance. In the present paper we will describe our view on the system-level optimization of high voltage GaN technology and present detailed simulations and comparison with experiments for both normally on isolated GaN transistors and cascoded GaN devices in real switching applications.

Off-state breakdown characteristics of AlGaN/GaN MIS-HEMTs for switching power applications

A consistent description of breakdown characteristics in ohmic-to-ohmic, ohmic-to-substrate and HEMT structures has been achieved by means of device simulations for a depletion-mode AlGaN/GaN MIS-HEMT technology on Si substrate suited for power switching applications. For relatively short gate-drain distances or ohmic-to-ohmic spacings, source-drain punch-through is suggested to be the limiting breakdown mechanism in either HEMTs under off-state conditions or ohmic-to-ohmic isolation test structures, respectively. The mechanism ultimately limiting the HEMT off-state voltage blocking capability is instead the vertical drain-to-substrate breakdown for long gate-drain spacings. The latter phenomenon is induced, in HEMTs on a low-resistivity p-type substrate like those considered here, by the triggering of a high-field carrier generation mechanism rather than by carrier injection.

Modelling of GaN HEMTs: From Device-Level Simulation to Virtual Prototyping

We describe an approach to modelling of power GaN HEMTs, aimed at full-system optimization through concurrent simulation of device, package, and application. We believe this “virtual prototyping” approach is an effective means to link fundamental understanding of the device properties to circuit- and system-level performance. Results are specifically presented from detailed simulations and comparison with experiments for both normally-on insulated-gate GaN HEMTs and normally-off pGaN devices in real switching applications.

Two-dimensional modeling of etched strained-silicon quantum wires

We present two-dimensional simulations of different types of strained-silicon quantum wires obtained by selective etching on silicon germanium heterostructures. Such structures are promising both for emerging ballistic devices in silicon compatible technology and for innovative nanoscale field-effect transistors. Numerical modeling has been performed with a procedure designed to solve the Poisson–Schrodinger equation for electrons and holes, that takes into account the effect of strain on the band structure, conduction band anisotropy, and the effect of states at the exposed surfaces. We show that the simulations provide insights into the capability to control the wire via an external gate voltage, and into the dependence of wire properties on geometry and surface states.