Oliver Häberlen

GaN-on-Si Power Technology: Devices and Applications

In this paper, we present a comprehensive reviewand discussion of the state-of-the-art device technology and application development of GaN-on-Si power electronics. Several device technologies for realizing normally off operation that is highly desirable for power switching applications are presented. In addition, the examples of circuit applications that can greatly benefit from the superior performance of GaN power devices are demonstrated. Comparisonwith other competingpower device technology, such as Si superjunction-MOSFET and SiC MOSFET, is also presented and analyzed. Critical issues for commercialization of GaN-on-Si power devices are discussed with regard to cost, reliability, and ease of use.

Influence of Buffer Carbon Doping on Pulse and AC Behavior of Insulated-Gate Field-Plated Power AlGaN/GaN HEMTs

Pulse behavior of insulated-gate double-field-plate power AlGaN/GaN HEMTs with C-doped buffers showing small current-collapse effects and dynamic RDS,on increase can accurately be reproduced by numerical device simulations that assume the CN-CGa autocompensation model as carbon doping mechanism. Current-collapse effects much larger than experimentally observed are instead predicted by simulations if C doping is accounted by dominant acceptor states. This suggests that buffer growth conditions favoring CN-CGa autocompensation can allow for the fabrication of power AlGaN/GaN HEMTs with reduced current-collapse effects. The drain-source capacitance of these devices is found to be a sensitive function of the C doping model, suggesting that its monitoring can be adopted as a fast technique to assess buffer compensation properties.

Simulation and inverse modeling of TEOS deposition processes using a fast level set method

Deposition and etching of silicon trenches is an important manufacturing step for state of the art memory cells. Understanding and simulating the transport of gas species and surface evolution enables to achieve void-less filling of deep trenches, to predict the resulting profiles, and thus to optimize process parameters with respect to manufacturing throughput and the quality of the resulting memory cells. For the simulation of the SiO/sub 2/ deposition process from TEOS (Tetraethoxysilane), the level set method was used in addition to physical models. The level set algorithm devised minimizes computational effort while ensuring high accuracy by intertwining narrow banding and extending the speed function. In order to make the predictions of the simulation more accurate, model parameters were extracted by comparing the step coverages of the deposited layers in the simulation with those of SEM (scanning electron microscope) images.

On Increasing the Accuracy of Simulations of Deposition and Etching Processes Using Radiosity and the Level Set Method

Deposition and etching in Silicon trenches is an important step of today’s semiconductor manufacturing. Understanding the surface evolution enables to predict the resulting profiles and thus to optimize process parameters. Simulations using the radiosity modeling approach and the level set method provide accurate results, but their speed has to be considered when employing advanced models and for purposes of inverse modeling. In this paper strategies for increasing the accuracy of deposition simulations while decreasing simulation times are presented. Two algorithms were devised: first, intertwining narrow banding and extending the speed function yields a fast and accurate level set algorithm. Second, an algorithm which coarsens the surface reduces the computational demands of the radiosity method. Finally measurements of a typical TEOS deposition process are compared with simulation results both with and without coarsening of the surface elements. It was found that the computational effort is significantly reduced without sacrificing the accuracy of the simulations.

Threshold voltage instabilities in D-mode GaN HEMTs for power switching applications

Threshold voltage instabilities observed in GaN HEMTs designed for power switching applications when submitted to either DC or pulsed testing are here presented and interpreted. Main results can be summarized as follows: i) two acceptor trap levels, characterized by two well distinct time constants, are present in the UID GaN channel and C-doped GaN buffer respectively and behave as electron and hole traps respectively; ii) the trapped charge is modulated by the high voltage biasing of the gate and drain terminals; iii) when empty, channel electron traps induce a negative threshold-voltage shift, while buffer hole traps induce a positive threshold-voltage shift; iv) when the device is pulsed from off- to on-state conditions, trap charge/discharge dynamics induces negative and positive threshold-voltage instabilities over distinct time scales.

Application specific trade-offs for WBG SiC, GaN and high end Si power switch technologies

There is an increasing choice of power switches in the 600V to 1700V range for the application engineers. Besides the well-established Si SJ (Super Junction) MOSFETs and IGBTs now also silicon carbide (SiC) and latest gallium nitride (GaN) power switches are available for new designs. Complete new system optimizations are possible driven by totally different trade off options e.g. between static and dynamic losses and their temperature dependencies. In this paper we explain these trade-offs for the different device types and show the consequences based on some prominent sample applications.

Emerging GaN-based HEMTs for mechanical sensing within harsh environments

Gallium nitride based high-electron-mobility transistors (HEMTs) have been investigated extensively as an alternative to Si-based power transistors by academia and industry over the last decade. It is well known that GaN-based HEMTs outperform Si-based technologies in terms of power density, area specific on-state resistance and switching speed. Recently, wide band-gap material systems have stirred interest regarding their use in various sensing fields ranging from chemical, mechanical, biological to optical applications due to their superior material properties. For harsh environments, wide bandgap sensor systems are deemed to be superior when compared to conventional Si-based systems. A new monolithic sensor platform based on the GaN HEMT electronic structure will enable engineers to design highly efficient propulsion systems widely applicable to the automotive, aeronautics and astronautics industrial sectors. In this paper, the advancements of GaN-based HEMTs for mechanical sensing applications are discussed. Of particular interest are multilayered heterogeneous structures where spontaneous and piezoelectric polarization between the interface results in the formation of a 2-dimensional electron gas (2DEG). Experimental results presented focus on the signal transduction under strained operating conditions in harsh environments. It is shown that a conventional AlGaN/GaN HEMT has a strong dependence of drain current under strained conditions, thus representing a promising future sensor platform. Ultimately, this work explores the sensor performance of conventional GaN HEMTs and leverages existing technological advances available in power electronics device research. The results presented have the potential to boost GaN-based sensor development through the integration of HEMT device and sensor design research.

The Role of Silicon Substrate on the Leakage Current Through GaN-on-Si Epitaxial Layers

We present an investigation of vertical leakage in GaN-on-Si epitaxial stack through electrical characterization and device simulations. Different structures of increasing complexity have been fabricated and analyzed in order to achieve a complete understanding of the main transport mechanisms. We have clarified the role of the Si substrate through comparison of identical structures built on p-type and n-type Si substrates. We show that in the case of p-Si substrates the leakage current is sustained by carrier generation in the Si depletion region. We also find that experiments on structures grown on n-doped silicon are consistent with considering electron injection from the substrate through the AlN/Si barrier as the main current limiting mechanism. Our insights are supported by device simulations that consistently reproduce the experimental capacitance–voltage and current–voltage characteristics as a function of temperature for all the considered structures.