Gilles Gervais

A streaming processing unit for a CELL processor

The design of a 4-way SIMD streaming data processor emphasizes achievable performance in area and power. Software controls data movement and instruction flow, and improves data bandwidth and pipeline utilization. The micro-architecture minimizes instruction latency and provides fine-grain clock control to reduce power.

The microarchitecture of the synergistic processor for a cell processor

This paper describes an 11 FO4 streaming data processor in the IBM 90-nm SOI-low-k process. The dual-issue, four-way SIMD processor emphasizes achievable performance per area and power. Software controls most aspects of data movement and instruction flow to improve memory system performance and core performance density. The design minimizes instruction latency while providing for fine grain clock control to reduce power.

Migration of Cell Broadband Engine from 65nm SOI to 45nm SOI

This paper describe the challenges of migrating the Cell Broadband Engine (Cell BE) design from a 65 nm SOI to a 45 nm twin-well CMOS technology on SOI with low-k dielectrics and copper metal layers using a mostly automated approach. A die micrograph of the 45 nm Cell BE is described here. The cycle-by-cycle machine behavior is preserved. The focuses are automated migration, power reduction, area reduction, and DFM improvements. The chip power is reduced by roughly 40% and the chip area is reduced by 34%.

Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI

This paper describes the architecture and implementation of the original gaming-oriented synergistic processor element (SPE) in both 90-nm and 65-nm silicon-on-insulator (SOI) technology and introduces a new SPE implementation targeted for the high-performance computing community. The Cell Broadband Engine™ processor contains eight SPEs. The dual-issue, four-way single-instruction multiple-data processor is designed to achieve high performance per area and power and is optimized to process streaming data, simulate physical phenomena, and render objects digitally. Most aspects of data movement and instruction flow are controlled by software to improve the performance of the memory system and the core performance density. The SPE was designed as an 11-F04 (fan-out-of-4-inverter-delay) processor using 20.9 million transistors within 14.8 mm 2 using the IBM 90-nm SOI low-k process. CMOS (complementary metal-oxide semiconductor) static gates implement the majority of the logic. Dynamic circuits are used in critical areas and occupy 19% of the non-static random access memory (SRAM) area. Instruction set architecture, microarchitecture, and physical implementation are tightly coupled to achieve a compact and power-efficient design. Correct operation has been observed at up to 5.6 GHz and 7.3 GHz, respectively, in 90-nm and 65-nm SOI technology.

Distributed On-chip Power Supply Noise Characterization of the Cell Broadband Engine

Noise characterization of the 65 nm multicore Cell Broadband Enginetrade (Cell/B.E.)* processor was performed using highly configurable workloads and selective stimulation of identical cores to study noise distribution throughout the chip. On-chip power supply noise propagation velocity and attenuation were found to be influenced by chip/package resonance in the power distribution system. Hypothesis for this phenomenon is proposed.

Power supply noise simulation considering dynamic effect of on-chip current

This paper describes a technique to analyze the dependence of on-chip switching current on power supply voltage and temperature, and how to implement that in power supply noise simulations. It is shown that this on-chip dynamic effect can introduce significant damping to the otherwise passive chip/package/board power supply network

Implementation of the 65nm Cell Broadband Engine

The first generation cell broadband engine processor introduced the cell architecture that consists of nine processor cores fabricated in the 90 nm CMOS SOI technology. This paper describes the advances made by moving the cell broadband engine design from 90 nm CMOS SOI to 65 nm CMOS SOI.