Sang Hoo Dhong

Custom 6-R, 2- or 4-W multi-port register files in an ASIC SOC with a DVFS window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS technology

We describe custom 6R, 2/4W general-purpose register files (GRF) in an ASIC-based SOC implemented in a N28 CMOS technology, which has roughly a 2~3 X smaller area, 2 X faster speed, and 5 X lower power than a logic-synthesized version. Synthesized and custom GRFs also have a different read behavior from static and dynamic circuitry used, respectively. This is addressed by modifying a bypass control block. Hardware showed a DVFS window of 0.5 V @circuit, 130 MHz to 0.96 V, 3.2 GHz.

A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS

This paper describes a tile-able 16-kByte 6-T SRAM macro in a High-K Metal-Gate (HKMG) 28-nm bulk technology with an operating window from 4.8 GHz at 1.12 V VDD down to 10 MHz at 0.5V, meeting almost all of the Dynamic Voltage Frequency Scaling (DVFS) requirements of Level-1 (L1) caches of a digital microprocessor SOC. It uses an unmodified technology-supported 0.156um2 high-current (HC) SRAM cell. Innovative and carefully optimized circuit solutions provide the wide operating range measured in hardware. We also discuss two circuit improvements, a cross-coupled PMOS-pair for each bitline-pair with mux readout and an independently-controlled precharge-and-write driver (ICPW), which gives a wider DVFS operating window with reduced sensitivities to Process-Voltage-Temperature (PVT) variations. Improved SRAM macros with new circuits have been designed and laid out and their performance and area verified in simulation.

Prospective for nanowire transistors

The multigate nanowire FET architecture allows for ultimate short-channel control and push Moores law down to sub-5nm gate lengths. This paper reviews nanowire transistor device physics as well as circuit prospects in the fields of CMOS logic, memory, analog, RF and integrated sensor applications.