Gina C. Adam

Training and operation of an integrated neuromorphic network based on metal-oxide memristors

Despite much progress in semiconductor integrated circuit technology, the extreme complexity of the human cerebral cortex, with its approximately 1014 synapses, makes the hardware implementation of neuromorphic networks with a comparable number of devices exceptionally challenging. To provide comparable complexity while operating much faster and with manageable power dissipation, networks based on circuits combining complementary metal-oxide-semiconductors (CMOSs) and adjustable two-terminal resistive devices (memristors) have been developed. In such circuits, the usual CMOS stack is augmented with one or several crossbar layers, with memristors at each crosspoint. There have recently been notable improvements in the fabrication of such memristive crossbars and their integration with CMOS circuits, including first demonstrations of their vertical integration. Separately, discrete memristors have been used as artificial synapses in neuromorphic networks. Very recently, such experiments have been extended to crossbar arrays of phase-change memristive devices. The adjustment of such devices, however, requires an additional transistor at each crosspoint, and hence these devices are much harder to scale than metal-oxide memristors, whose nonlinear current–voltage curves enable transistor-free operation. Here we report the experimental implementation of transistor-free metal-oxide memristor crossbars, with device variability sufficiently low to allow operation of integrated neural networks, in a simple network: a single-layer perceptron (an algorithm for linear classification). The network can be taught in situ using a coarse-grain variety of the delta rule algorithm to perform the perfect classification of 3 × 3-pixel black/white images into three classes (representing letters). This demonstration is an important step towards much larger and more complex memristive neuromorphic networks.

Optimized stateful material implication logic for three-dimensional data manipulation

The monolithic three-dimensional integration of memory and logic circuits could dramatically improve the performance and energy efficiency of computing systems. Some conventional and emerging memories are suitable for vertical integration, including highly scalable metal-oxide resistive switching devices (“memristors”). However, the integration of logic circuits has proven to be much more challenging than expected. In this study, we demonstrated memory and logic functionality in a monolithic three-dimensional circuit by adapting the recently proposed memristor-based stateful material implication logic. By modifying the original circuit to increase its robustness to device imperfections, we experimentally showed, for the first time, a reliable multi-cycle multi-gate material implication logic operation and half-adder circuit within a threedimensional stack of monolithically integrated memristors. Direct data manipulation in three dimensions enables extremely compact and high-throughput logicin- memory computing and, remarkably, presents a viable solution for the Feynman Grand Challenge of implementing an 8-bit adder at the nanoscale.

Modeling and implementation of firing-rate neuromorphic-network classifiers with bilayer Pt/Al2O3/TiO2−x/Pt Memristors

Neuromorphic pattern classifiers were implemented, for the first time, using transistor-free integrated crossbar circuits with bilayer metal-oxide memristors. 10×6- and 10×8-crosspoint neuromorphic networks were trained in-situ using a Manhattan-Rule algorithm to separate a set of 3×3 binary images: into 3 classes using the batch-mode training, and into 4 classes using the stochastic-mode training, respectively. Simulation of much larger, multilayer neural network classifiers based on such technology has sown that their fidelity may be on a par with the state-of-the-art results for software-implemented networks.

Spiking neuromorphic networks with metal-oxide memristors

This is a brief review of our recent work on memristor-based spiking neuromorphic networks. We first describe the recent experimental demonstration of several most biology-plausible spike-time-dependent plasticity (STDP) windows in integrated metal-oxide memristors and, for the first time, the observed self-adaptive STDP, which may be crucial for spiking neural network applications. We then discuss recent theoretical work in which an analytical, data-verified STDP model was used to simulate operation of a spiking classifier of spatial-temporal patterns, and the capacity-to-fidelity tradeoff and noise immunity o f spiking spatial-temporal associative memories with local and global recording was evaluated.

Stateful characterization of resistive switching TiO 2 with electron beam induced currents

Metal oxide resistive switches are increasingly important as possible artificial synapses in next-generation neuromorphic networks. Nevertheless, there is still no codified set of tools for studying properties of the devices. To this end, we demonstrate electron beam-induced current measurements as a powerful method to monitor the development of local resistive switching in TiO2-based devices. By comparing beam energy-dependent electron beam-induced currents with Monte Carlo simulations of the energy absorption in different device layers, it is possible to deconstruct the origins of filament image formation and relate this to both morphological changes and the state of the switch. By clarifying the contrast mechanisms in electron beam-induced current microscopy, it is possible to gain new insights into the scaling of the resistive switching phenomenon and observe the formation of a current leakage region around the switching filament. Additionally, analysis of symmetric device structures reveals propagating polarization domains.Oxide-based memristors hold promise for artificial neuromorphic computing, yet the detail of the switching mechanism—filament formation—remains largely unknown. Hoskins et al. provide nanoscale imaging of this process using electron beam induced current microscopy and relate it to resistive states.

Highly-uniform multi-layer ReRAM crossbar circuits

Resistive switching memories have been identified as an enabling technology for a variety of emerging computing applications, including neuromorphic and logic-in-memory computing. For example, analog tuning of the memory state combined with high integration density of memristors is needed for very compact implementation of synapses, the most numerous devices in artificial neural networks and would be essential for low energy implementations of large-scale neuromorphic circuits. One way to increase effective memristor density is by vertical monolithical integration of memristor crossbar circuits. Previous work on such circuits have focused on their use for digital memory applications. Only limited device statistics was typically reported, not sufficient for understanding prospects for computing applications. Here we report fabrication and detailed characterization results for a bilayer stacked metal-oxide memristor crossbar circuits. The experimental results show excellent uniformity for the memristors in both crossbar layers. Moreover, the utilized low temperature process flow is CMOS compatible and can be extended to multi-layer stacking.

Publisher Correction: Stateful characterization of resistive switching TiO2 with electron beam induced currents

The original version of this Article contained an error in Eq. 1. The arrows between the symbols “T” and “B”, and “B” and “T”, were written “↔” but should have been “→”, and incorrectly read: IEBIC=IEBAC+ISEE+I(e↔h)+IEBICT↔B+IESEEB↔T The correct from of the Eq. 1 is as follows:IEBIC=IEBAC+ISEE+I(e↔h)+IEBICT→B+IESEEB→T This has now been corrected in both the PDF and HTML versions of the article.

Two artificial synapses are better than one

Emerging nanoelectronic devices could revolutionize artificial neural networks, but their hardware implementations lag behind those of their software counterparts. An approach has been developed that tips the scales in their favour.Emerging nanoelectronic devices could revolutionize artificial neural networks, but their hardware implementations lag behind those of their software counterparts. An approach has been developed that tips the scales in their favour.

3D ReRAM arrays and crossbars: Fabrication, characterization and applications

As the rapid progress of memristor technology continues, multi-layer stacking of these crossbars is needed in order to maximize the use of vertical space and achieve the required density for high throughput applications. This work summarizes our efforts of designing and building three-dimensional monolithically integrated memristive arrays and crossbars, both standalone and onto CMOS chips. We discuss the fabrication and electrical characterization details of stand-alone and CMOS integrated ReRAM arrays and crossbars together with their use in experimental demonstrations of digital and analog applications such as three-dimensional stateful logic, hardware security primitives and dot-product operations.

Micro- and Macroscale Ideas of Current Among Upper-Division Electrical Engineering Students

The concept of electric current is fundamental in the study of electrical engineering (EE). Students are often exposed to this concept in their daily lives and early in middle school education. Lower-division university courses are usually limited to the study of passive electronic devices and simple electric circuits. Semiconductor physics is an upper-division course that presents the physics behind semiconductor devices in depth and exposes the students to microscale explanations of different types of current, such as drift and diffusion currents. This paper investigates how third-year college students majoring in EE link microscale and macroscale concepts of current, and what misconceptions they reveal after one quarter of advanced instruction in semiconductor physics. The interviewees were posed a problem, based on a distracting device structure that exposed student difficulties in defining current, charges and doping, and the plotting of current–voltage (I–V) characteristics. For example, some students had the naïve idea that current is the flow of a particular type of charge (i.e., only electrons or only holes) or that there is a “spectrum of doping.” Almost all students drew a one-quadrant coordinate system for the I–V curves, which might imply that students think only about positive voltages. These findings can inform further studies to identify and address misconceptions in the important area of semiconductor device physics.