Mirko Prezioso

Training and operation of an integrated neuromorphic network based on metal-oxide memristors

Despite much progress in semiconductor integrated circuit technology, the extreme complexity of the human cerebral cortex, with its approximately 1014 synapses, makes the hardware implementation of neuromorphic networks with a comparable number of devices exceptionally challenging. To provide comparable complexity while operating much faster and with manageable power dissipation, networks based on circuits combining complementary metal-oxide-semiconductors (CMOSs) and adjustable two-terminal resistive devices (memristors) have been developed. In such circuits, the usual CMOS stack is augmented with one or several crossbar layers, with memristors at each crosspoint. There have recently been notable improvements in the fabrication of such memristive crossbars and their integration with CMOS circuits, including first demonstrations of their vertical integration. Separately, discrete memristors have been used as artificial synapses in neuromorphic networks. Very recently, such experiments have been extended to crossbar arrays of phase-change memristive devices. The adjustment of such devices, however, requires an additional transistor at each crosspoint, and hence these devices are much harder to scale than metal-oxide memristors, whose nonlinear current–voltage curves enable transistor-free operation. Here we report the experimental implementation of transistor-free metal-oxide memristor crossbars, with device variability sufficiently low to allow operation of integrated neural networks, in a simple network: a single-layer perceptron (an algorithm for linear classification). The network can be taught in situ using a coarse-grain variety of the delta rule algorithm to perform the perfect classification of 3 × 3-pixel black/white images into three classes (representing letters). This demonstration is an important step towards much larger and more complex memristive neuromorphic networks.

Electrically Programmable Magnetoresistance in Multifunctional Organic-Based Spin Valve Devices

5] In this paper we show that an electrically controlled magne-toresistance can be easily achieved in organic devices by com-bining magnetic bistability (spin valve) and electrical memory effects into an interacting multifunctional implementation. Electrical resistive switching effects in organic-based devices have recently received widespread attention

A Single-Device Universal Logic Gate Based on a Magnetically Enhanced Memristor

Memristors are one of the most promising candidates for future information and communications technology (ICT) architectures. Two experimental proofs of concept are presented based on the intermixing of spintronic and memristive effects into a single device, a magnetically enhanced memristor (MEM). By exploiting the interaction between the memristance and the giant magnetoresistance (GMR), a universal implication (IMP) logic gate based on a single MEM device is realized.

Self-Adaptive Spike-Time-Dependent Plasticity of Metal-Oxide Memristors

Metal-oxide memristors have emerged as promising candidates for hardware implementation of artificial synapses – the key components of high-performance, analog neuromorphic networks - due to their excellent scaling prospects. Since some advanced cognitive tasks require spiking neuromorphic networks, which explicitly model individual neural pulses (“spikes”) in biological neural systems, it is crucial for memristive synapses to support the spike-time-dependent plasticity (STDP). A major challenge for the STDP implementation is that, in contrast to some simplistic models of the plasticity, the elementary change of a synaptic weight in an artificial hardware synapse depends not only on the pre-synaptic and post-synaptic signals, but also on the initial weight (memristor’s conductance) value. Here we experimentally demonstrate, for the first time, an STDP behavior that ensures self-adaptation of the average memristor conductance, making the plasticity stable, i.e. insensitive to the initial state of the devices. The experiments have been carried out with 200-nm Al2O3/TiO2−x memristors integrated into 12 × 12 crossbars. The experimentally observed self-adaptive STDP behavior has been complemented with numerical modeling of weight dynamics in a simple system with a leaky-integrate-and-fire neuron with a random spike-train input, using a compact model of memristor plasticity, fitted for quantitatively correct description of our memristors.

Hanle effect missing in a prototypical organic spintronic device

We investigate spin precession (Hanle effect) in the prototypical organic spintronic giant magnetoresistance device La0.7Sr0.3MnO3/tris(8-hydroxyquinoline)/AlOx/Co. The Hanle effect is not observed in measurements taken by sweeping a magnetic field at different angles from the plane of the device. As possible explanations we discuss the tilting out of plane of the magnetization of the electrodes, exceptionally high mobility, or hot spots. Our results call for a greater understanding of spin injection and transport in such devices.

Regenerable Resistive Switching in Silicon Oxide Based Nanojunctions

A nanomemristor based on SiO(2) is fabricated in situ with spatial control at the nanoscale. The proposed system exhibits peculiar properties such as the possibility to be regenerated after being stressed or damaged and the possibility to expose the metal and the oxide interfaces by removing the top electrodes.

Tunnel conductivity switching in a single nanoparticle-based nano floating gate memory

Nanoparticles (NPs) embedded in a conductive or insulating matrix play a key role in memristors and in flash memory devices. However, the role of proximity to the interface of isolated NPs has never been directly observed nor fully understood. Here we show that a reversible local switching in tunnel conductivity can be achieved by applying an appropriate voltage pulse using the tip of a scanning tunnelling microscope on NPs embedded in a TiO2 matrix. The resistive switching occurs in the TiO2 matrix in correlation to the NPs that are in proximity of the surface and it is spatially confined to the single NP size. The tunnel conductivity is increased by more than one order of magnitude. The results are rationalized by a model that include the charge of NPs that work as a nano floating gate inducing local band bending that facilitates charge tunnelling and by the formation and redistribution of oxygen vacancies that concentrate in proximity of the charged NPs. Our study demonstrates the switching in tunnel conductivity in single NP and provides useful information for the understanding mechanism or resistive switching.

Optimized stateful material implication logic for three-dimensional data manipulation

The monolithic three-dimensional integration of memory and logic circuits could dramatically improve the performance and energy efficiency of computing systems. Some conventional and emerging memories are suitable for vertical integration, including highly scalable metal-oxide resistive switching devices (“memristors”). However, the integration of logic circuits has proven to be much more challenging than expected. In this study, we demonstrated memory and logic functionality in a monolithic three-dimensional circuit by adapting the recently proposed memristor-based stateful material implication logic. By modifying the original circuit to increase its robustness to device imperfections, we experimentally showed, for the first time, a reliable multi-cycle multi-gate material implication logic operation and half-adder circuit within a threedimensional stack of monolithically integrated memristors. Direct data manipulation in three dimensions enables extremely compact and high-throughput logicin- memory computing and, remarkably, presents a viable solution for the Feynman Grand Challenge of implementing an 8-bit adder at the nanoscale.

Modeling and implementation of firing-rate neuromorphic-network classifiers with bilayer Pt/Al2O3/TiO2−x/Pt Memristors

Neuromorphic pattern classifiers were implemented, for the first time, using transistor-free integrated crossbar circuits with bilayer metal-oxide memristors. 10×6- and 10×8-crosspoint neuromorphic networks were trained in-situ using a Manhattan-Rule algorithm to separate a set of 3×3 binary images: into 3 classes using the batch-mode training, and into 4 classes using the stochastic-mode training, respectively. Simulation of much larger, multilayer neural network classifiers based on such technology has sown that their fidelity may be on a par with the state-of-the-art results for software-implemented networks.

Memory Technologies for Neural Networks

Synapses, the most numerous elements of neural networks, are memory devices. Similarly to traditional memory applications, device density is one of the most essential metrics for large-scale artificial neural networks. This application, however, imposes a number of additional requirements, such as the continuous change of the memory state, so that novel engineering approaches are required. In this paper, we briefly review our recent efforts at addressing these needs. We start by reviewing the CrossNet concept, which was conceived to address major challenges of artificial neural networks. We then discuss the recent progress toward CrossNet implementation, in particular the experimental results for simple networks with crossbar-integrated resistive switching (memristive) metal oxide devices. Finally, we review preliminary results on redesigning commercial-grade embedded NOR flash memories to enable individual cell tuning. While NOR flash memories are less dense then memristor crossbars, their technology is much more mature and ready for the development of large-scale neural networks.