Giorgio Betti

A 200 MSample/s trellis-coded PRML read/write channel with digital servo

A fully-integrated R/W IC operates at 200 MSample/s channel rate and supports two recording codes: a rate 4/5 (0,4/8) matched spectral null (MSN) trellis code and associated detector, and a rate 8/9 (0,4/4) with a standard maximum-likelihood PR4 detector. The chip supports a complete flexible digital servo and four-level write precompensation to overcome media nonlinearity. The device is integrated in 0.7 /spl mu/m BiCMOS technology, has 54 mm/sup 2/ die and uses 2 W with MSN code or 1.5 W with PR4 code at 4.5 V and 200 MSample/s. This chip avoids external interface chips, incorporating an ADC and functions useful to the servo DSP. MSN code provides approximately 2 dB gain in SNR with respect to rate 8/9 PR4 coding at a user density of PW/sub 50//T/sub max/=1.8.

Session 23 Overview: Channel Coding

Advances in communications and storage ICs are discussed in this session. These ICs play a key role in the multimedia era, for which high-rate access everywhere, and almost-infinite storage capabilities for consumers, are both in high demand. In the communications (wireless and wireline) domain, the main challenge is to maximize information transfer for a certain energy budget. In the storage domain, the main challenge for both magnetic and optical media is to maximize the number of bits per unit of area at a reasonable cost. Both requirements demand new algorithms and more computing power. Since channel coding has been applied to mass products, significant decreases in product cost are reported. This is achieved by continuously migrating products to more advanced process technology, while increasing the level of integration. Use of multistandard capabilities offers high flexibility and further cost reduction. In the first four papers, channel-coding ICs in the area of communications are presented. In Paper 23.1 a 600MHz DSP with a flexible programmable architecture, tuned for 3G basestation applications and integrated with a 24Mb embedded DRAM, is described. Paper 23.2 presents a MIMO high-speed downlink packet access receiver able to process up to 28.8Mb/s using QPSK, offering 5.76b/s/Hz. In Paper 23.3 a highly integrated CDMA2000 baseband IC including an embedded ARM and two DSP processors, offering multistandard and multimedia capabilities is presented. Finally, Paper 23.4 describes a 350Mb/s turbo-codec based on 16-state SISO decoders. In the second part of the session, three papers describe advances in coding and processing for storage. In Paper 23.5, an SoC for the Blu-ray disc standard is presented which features an integration level compatible with consumer applications. In Paper 23.6, a high level of integration supporting multistandard optical-storage CD/DVD play back and CD-R/RW recording is described. In Paper 23.7 decision-feedback equalization is applied to improve robustness of the timing-recovery loop for a General Partial Response magnetic-storage front-end.