Marco Cazzaniga
STMicroelectronics
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Publication
Featured researches published by Marco Cazzaniga.
IEEE Journal of Solid-state Circuits | 1997
Francesco Rezzi; Ivan Bietti; Marco Cazzaniga; R. Castello
A seventh-order phase equiripple continuous time filter implementing pulse shaping and noise filtering for partial response maximum likelihood (PRML) read channel applications is presented. The 7-50 MHz cutoff frequency, amount of boost, and group-delay slope are programmable via 7-b digital-to-analog converters (DACs). At 50 MHz fc, power consumption is 70 mW and output swing for 1% distortion is more than 500 mVpp. The transconductance capacitance (Gm-C) filter is built in a 0.7-/spl mu/m 10-GHz BiCMOS technology.
Archive | 1996
Frencesco Rezzi; R. Castello; Marco Cazzaniga; Ivan Bietti
Archive | 2001
Valerio Pisati; Augusto Rossi; Giorgio Betti; Marco Cazzaniga
Archive | 2001
Valerio Pisati; Marco Cazzaniga; Alessandro Venca
Archive | 2001
Valerio Pisati; Salvatore Portaluri; Marco Cazzaniga; R. Castello
Archive | 2007
Valerio Pisati; Augusto Rossi; Giorgio Betti; Marco Cazzaniga
Archive | 2001
Valerio Pisati; Salvatore Portaluri; Marco Cazzaniga; R. Castello
Archive | 2001
R. Castello; Marco Cazzaniga; Valerio Pisati; Salvatore Portaluri
Archive | 2001
Valerio Pisati; Salvatore Portaluri; Marco Cazzaniga; R. Castello
Archive | 2000
Valerio Pisati; Augusto Rossi; Giorgio Betti; Marco Cazzaniga