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Dive into the research topics where Girolamo Gallo is active.

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Featured researches published by Girolamo Gallo.


international solid-state circuits conference | 2016

7.7 A 768Gb 3b/cell 3D-floating-gate NAND flash memory

Tomoharu Tanaka; Mark A. Helm; Tommaso Vali; Ramin Ghodsi; Koichi Kawai; Jae-Kwan Park; Shigekazu Yamada; Feng Pan; Yuichi Einaga; Ali Ghalam; Toru Tanzawa; Jason Guo; Takaaki Ichikawa; Erwin Yu; Satoru Tamada; Tetsuji Manabe; Jiro Kishimoto; Yoko Oikawa; Yasuhiro Takashima; Hidehiko Kuge; Midori Morooka; Ali Mohammadzadeh; Jong Kang; Jeff Tsai; Emanuele Sirizotti; Eric N. Lee; Luyen Vu; Yuxing Liu; Hoon Choi; Kwonsu Cheon

A planar floating-gate NAND technology has previously realized a 0.87Gb/mm2 memory density using 3b/cell [1] and achieved a minimum feature size for 16nm [2]. However, the development of planar NAND flash is expected to reach the scaling limit in a few technology generations. To break though this limit, a significant shift to 3D NAND flash has begun and several types of 3D memory cell structures have been proposed and discussed [3-5]. Recently a 3D V-NAND technology achieved 1.86Gb/mm2 using charge-trap cells and 3b/cell [6]. This paper presents a 3b/cell NAND flash memory utilizing a 3D floating gate (FG) technology that achieves 4.29Gb/mm2.


international solid-state circuits conference | 2013

A 128Gb 3b/cell NAND flash design using 20nm planar-cell technology

Giovanni Naso; L. Botticchio; M. Castelli; C. Cerafogli; M. Cichocki; P. Conenna; Andrea D'Alessandro; Luca De Santis; Domenico Di Cicco; W. D. Francesco; M. L. Gallese; Girolamo Gallo; Michele Incarnati; C. Lattaro; Agostino Macerola; Giulio Marotta; Violante Moschiano; D. Orlandi; F. Paolini; S. Perugini; Luigi Pilolli; P. Pistilli; G. Rizzo; F. Rori; Massimo Rossini; Giovanni Santin; E. Sirizotti; A. Smaniotto; U. Siciliani; Marco-Domenico Tiburzi

The authors develop a 128Gb 3b/cell NAND Flash memory based on 20nm fully planar cell process technology. The planar cell allows the memory cell to be scaled in both the wordline (WL) and bitline (BL) directions, resulting in a small 3b/cell memory device. The sensing scheme is based on a ramping technique that allows the detection of hard and soft states in a single operation.


Archive | 2008

Low power multiple bit sense amplifier

Girolamo Gallo; Giulio Marotta


Archive | 2006

Variable impedence output buffer

Girolamo Gallo; Giulio Marotta


Archive | 2004

Fast sensing scheme for floating-gate memory cells

Girolamo Gallo; Tommaso Vali; Giulio Marotta


Archive | 2003

Dual bus memory burst architecture

Girolamo Gallo; Giuliano Gennaro Imondi; Giovanni Naso; Tommaso Vali


Archive | 2006

Output buffer strength trimming

Girolamo Gallo; Giulio Marotta; Giovanni Naso


Archive | 2006

Variable impedance output buffer

Girolamo Gallo; Giulio Marotta


Archive | 2006

Leseverstärker mit niedriger leistung und mehreren bits

Giulio Marotta; Girolamo Gallo


Archive | 1995

Method for recognizing character and its device

Girolamo Gallo; Cristina Lattaro; Giuseppe Savarese; ガロ ギロラモ; ラッタロ クリスティナ; サバレセ ジウゼッペ

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