Gisele Martin-Chassard

The OPERA experiment Target Tracker

The main task of the Target Tracker detector of the long baseline neutrino oscillation OPERA experiment is to locate in which of the target elementary constituents, the lead/emulsion bricks, the neutrino interactions have occurred and also to give calorimetric information about each event. The technology used consists in walls of two planes of plastic scintillator strips, one per transverse direction. Wavelength shifting fibres collect the light signal emitted by the scintillator strips and guide it to both ends where it is read by multi-anode photomultiplier tubes. All the elements used in the construction of this detector and its main characteristics are described.

SKIROC2, front end chip designed to readout the Electromagnetic CALorimeter at the ILC

SKIROC (Silicon Kalorimeter Integrated ReadOut Chip) is the front end chip designed for the readout of the Silicon PIN diodes foreseen for the Electromagnetic CALorimeter (ECAL) at the future International Linear Collider. The fine granularity of the ILC calorimeters implies an extremely large number of electronics channels (82 millions) which is a new feature of ``imaging calorimetry. Moreover, for compactness, the chips must be embedded inside the detector without any external component making essential the reduction of the power consumption to 25 μWatt per channel. This is achieved using power pulsing, made possible by the ILC bunch pattern (1 ms of acquisition data for 199 ms of dead time).

HARDROC: Readout chip for CALICE/EUDET Digital Hadronic Calorimeter

HARDROC [1] (HAdronic Rpc Detector Read Out Chip) is the very front end chip designed for the readout of the RPC or Micromegas foreseen for the Digital HAdronic CALorimeter (DHCAL) of the future International Linear Collider and designed within the CALICE collaboration [2]. The very fine granularity of the ILC hadronic calorimeters (1cm2 pads) implies a huge number of electronics channels (4 105 /m3) which is a new feature of “imaging” calorimetry. Moreover, for compactness, the chips must be embedded inside the detector making crucial the reduction of the power consumption to 10 μWatt per channel. This is achieved using power pulsing, made possible by the ILC bunch pattern (1 ms of acquisition data for 199 ms of dead time). HARDROC readout is a semi-digital readout with three thresholds which allows both good tracking and coarse energy measurement, and also integrates on chip data storage. The overall performance of HARDROC will be described with detailed measurements of all the characteristics. Hundreds of chips have indeed been produced and tested before being mounted on printed boards developed for the readout of large scale (1m2) RPC and Micromegas prototypes. These prototypes have been tested with cosmics and also in testbeam at CERN between 2008 and 2010 to evaluate the performance of different kinds of GRPCs and to validate the semi-digital electronics readout system in beam conditions. A production of 10 000 chips has been launched in March 2010 to equip 40 GRPC planes (400 000 channels) of a 1 cubic meter detector that will be tested in 2011.

PARISROC, a photomultiplier array integrated read out chip

PARISROC is a complete read out chip, in AMS SiGe 0.35 μm technology, for photomultipliers array. It allows triggerless acquisition for next generation neutrino experiments and it belongs to an R&D program funded by the French national agency for research (ANR) called PMm2: “Innovative electronics for photodetectors array used in High Energy Physics and Astroparticles” (ref.ANR-06-BLAN-0186). The ASIC (Application Specific Integrated Circuit) integrates 16 independent and auto triggered channels with variable gain and provides charge and time measurement by a Wilkinson ADC (Analog to Digital Converter) and a 24-bit Counter. The charge measurement should be performed from 1 up to 300 photo-electrons (p.e.) with a good linearity. The time measurement allowed to a coarse time with a 24-bit counter at 10 MHz and a fine time on a 100ns ramp to achieve a resolution of 1 ns. The ASIC sends out only the relevant data through network cables to the central data storage. This paper describes the front-end electronics ASIC called PARISROC.

MICROROC: MICRO-mesh gaseous structure Read-Out Chip

MICRO MEsh GAseous Structure (MICROMEGAS) and Gas Electron Multipliers (GEM) detectors are two candidates for the active part of a Digital Hadronic CALorimeter (DHCAL) as part of a high energy physics experiment at the International Linear Collider. Physics requirements lead to a highly granular hadronic calorimeter with up to thirty million channels with probably only hit information (digital calorimeter). To validate the concept of digital hadronic calorimetry, a cubic meter technological prototype, made of 40 planes of one squared meter each, is compulsory. Such a technological prototype involves not less than 400 000 electronic channels, thus requiring the development of ASIC. Based on the experience of previous ASICs (DIRAC and HARDROC) and on multiple testbeam results, a new ASIC, called MICROROC (MICRO mesh gaseous structure Read-Out Chip), is currently beeing jointly developped at IN2P3 by OMEGA/LAL and LAPP microelectronics goups. It should be submitted to foundry in june 2010, and prototypes are expected to be delivred at the beginning of september. MICROROC is a 64 channel mixed-signal integrated circuit based on HARDROC manufactured in AMS 350 nm SiGe technology. Analog blocks and the whole digital part are reused from HARDROC, but the very front-end part, ie the preamplifier and shapers, has been especially re-designed for one square meter MICROMEGAS detectors, which require HV sparks robustness for the electronics and also very low noise performance to detect signals down to 2fC with an anode capacitance of. Each channel of the MICROROC chip is made of a fixed gain charge preamplifier, two different adjustable shapers, three comparators and a random access memory used as a digital buffer. Other blocks, like 12-bit DAC, configuration registers, bandgap voltage reference and LVDS receiver are included. All these blocks are power-pulsed, thus reaching a power consumption equal to zero in standby mode. After characterisation of the MPW prototypes, a low volume production will be packaged in TQFP160 with the same pinout as the HARDROC chip. Therefore bulk MICROMEGAS detectors with embedded MICROROC will be straightforward built, using HARDROC previously designed PCBs and the same data acquisition system.

SPACIROC: A front-end readout ASIC for the JEM-EUSO observatory

The SPACIROC ASIC is designed for the JEMEUSO observatory onboard of the International Space Station (ISS). The main goal of JEM-EUSO is to observe Extensive Air Shower (EAS) produced in the atmosphere by the passage of the high energetic extraterrestrial particles above a few 10^19 eV. A low-power, rad-hard ASIC is proposed for reading out the 64-channel Multi-Anode Photomultipliers which will equip the detection surface of JEM-EUSO. Two main features of this ASIC are the photon counting mode for each input and the charge-totime (Q-to-T) conversion for the multiplexed channels. In the photon counting mode, the 100% triggering efficiency is achieved for 50 fC input charges. For the Q-to-T converter, the ASIC requires a minimum input of 2 pC. In order to comply with the strict power budget available from the ISS, the ASIC is needed to dissipate less than 1 mW/channel. The design of SPACIROC and the test results are presented in this paper. SPACIROC is a result of the collaboration between OMEGA/LAL-Orsay, France, RIKEN, ISAS/JAXA and Konan University, Japan on behalf of the JEM-EUSO consortium.

Digital part of PARISROC2: a photomultiplier array readout chip

PARISROC is the front end ASIC designed to read 16 PMT for neutrino experiments. It’s able to shape, discriminate, convert and readout data in an autonomous mode. The digital part manages each channel independently thanks to 4 modules: top manager, acquisition, conversion and readout. Acquisition is in charge to manage the SCA with a depth of 2 for charge and fine time measurement. Coarse time measurement is made with a 24 bits gray counter. Readout module sends converted data of hit channels to an external system. Top manager controls the start and stop of the 3 others modules. The ASIC was submitted in June 2008.

PMm2: R&D on triggerless acquisition for next generation neutrino experiments

The next generation of proton decay and neutrino experiments, the post-SuperKamiokande detectors, such as those that will take place in megaton size water tanks, will require very large surfaces of photo-detection and will produce a large volume of data. Even with large hemispherical photomultiplier tubes (PMTs), the expected number of channels should reach hundreds of thousands. An ANR funded R&D program to implement a solution is presented here. The very large surface of photo-detection is segmented in macro pixels consisting of an array (2 × 2 m2) of 16 hemispherical 12-inch PMTs connected to autonomous underwater front-end electronics working in a triggerless data acquisition mode. The array is powered by a common high voltage and only one data cable allows the connection by network to the surface controller. This architecture allows a considerable reduction of the cost and facilitates the industrialization. This paper presents the complete architecture of the prototype system and tests results with 16 8-inch PMTs, validating the whole electronics, the built-in gain adjustment and the calibration principle.

SPACIROC2: A front-end readout ASIC for the JEM-EUSO observatory

The SPACIROC ASIC is designed for the JEMEUSO observatory onboard of the International Space Station (ISS). The main goal of JEM-EUSO is to observe Extensive Air Shower (EAS) produced in the atmosphere by the passage of the high energetic extraterrestrial particles above a few 10^19 eV. A low-power, rad-hard ASIC is proposed for reading out the 64-channel Multi-Anode Photomultipliers which will equip the detection surface of JEM-EUSO. Two main features of this ASIC are the photon counting mode for each input and the charge-totime (Q-to-T) conversion for the multiplexed channels. In the photon counting mode, the 100% triggering efficiency is achieved for 50 fC input charges. For the Q-to-T converter, the ASIC requires a minimum input of 2 pC. In order to comply with the strict power budget available from the ISS, the ASIC is needed to dissipate less than 1 mW/channel. The design of SPACIROC and the test results are presented in this paper. SPACIROC is a result of the collaboration between OMEGA/LAL-Orsay, France, RIKEN, ISAS/JAXA and Konan University, Japan on behalf of the JEM-EUSO consortium.

Triroc: 64-channel SiPM read-out ASIC for PET/PET- ToF application

Triroc is the latest addition to SiPM readout ASICs family developed at Weeroc, a start-up company from the Omega microelectronics group of IN2P3/CNRS. This chip developed under the framework TRIMAGE European project which is aimed for building a cost effective trimodal PET/MR/EEG brain scan. To ensure the flexibility and compatibility with any SiPM in the market, the ASIC is designed to be capable of accepting negative and positive polarity input signals.