S. Conforti Di Lorenzo

PARISROC, a photomultiplier array integrated read out chip

PARISROC is a complete read out chip, in AMS SiGe 0.35 μm technology, for photomultipliers array. It allows triggerless acquisition for next generation neutrino experiments and it belongs to an R&D program funded by the French national agency for research (ANR) called PMm2: “Innovative electronics for photodetectors array used in High Energy Physics and Astroparticles” (ref.ANR-06-BLAN-0186). The ASIC (Application Specific Integrated Circuit) integrates 16 independent and auto triggered channels with variable gain and provides charge and time measurement by a Wilkinson ADC (Analog to Digital Converter) and a 24-bit Counter. The charge measurement should be performed from 1 up to 300 photo-electrons (p.e.) with a good linearity. The time measurement allowed to a coarse time with a 24-bit counter at 10 MHz and a fine time on a 100ns ramp to achieve a resolution of 1 ns. The ASIC sends out only the relevant data through network cables to the central data storage. This paper describes the front-end electronics ASIC called PARISROC.

SPIROC: design and performances of a dedicated very front-end electronics for an ILC Analog Hadronic CALorimeter (AHCAL) prototype with SiPM read-out

For the future e+ e- International Linear Collider (ILC) the ASIC SPIROC (Silicon Photomultiplier Integrated Read-Out Chip) was designed to read out the Analog Hadronic Calorimeter (AHCAL) equipped with Silicon Photomultiplier (SiPM). It is an evolution of the FLC_SiPM chip designed by the OMEGA group in 2005. SPIROC2 [1] was realized in AMS SiGe 0.35 μm technology [2] and developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of read-out channels. This ASIC is a very front-end read-out chip that integrates 36 self triggered channels with variable gain to achieve charge and time measurements. The charge measurement must be performed from 1 up to 2000 photo-electrons (p.e.) corresponding to 160 fC up to 320 pC for SiPM gain 106. The time measurement is performed with a coarse 12-bit counter related to the bunch crossing clock (up to 5 MHz) and a fine time ramp based on this clock (down to 200 ns) to achieve a resolution of 1 ns. An analog memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. The analog memory content (time and charge) is digitized thanks to an internal 12-bit Wilkinson ADC. The data is then stored in a 4kbytes RAM. A complex digital part is necessary to manage all these features and to transfer the data to the DAQ. SPIROC2 is the second generation of the SPIROC ASIC family designed in 2008 by the OMEGA group. A very similar version (SPIROC2c) was submitted in February 2012 to improve the noise performance and also to integrate a new TDC (Time to Digital Converter) structure. This paper describes SPIROC2 and SPIROC2c ASICs and illustrates the main characteristics thank to a series of measurements.

Subnano time to digital converter implemented in PARISROC for PMm2 R&D program

PARISROC is a complete read out chip, in a BiCMOS SiGe 0.35μm technology from AustriaMicroSystems, for photomultipliers array. It allows triggerless acquisition for next generation neutrino experiments and is part of a R&D program called PMm2. The ASIC integrates 16 independent and auto triggered channels with variable gain and provides charge and time measurement by a 10-bit Wilkinson ADC and a 24-bit counter. The time measurement is made of 2 complementary systems: a 24-bit gray counter (coarse time) with a step of 100 ns, and a double ramp TDC (fine time) with a 10-bit resolution and a measured precision of 425 ps RMS. Only the analog TDC will be explained in this paper by detailing the double ramp TDC architecture, the special cares and the first fine time measurements. One of the fine time TDC characteristics is the fact that the double ramp generator is common to all channels.

Digital part of PARISROC2: a photomultiplier array readout chip

PARISROC is the front end ASIC designed to read 16 PMT for neutrino experiments. It’s able to shape, discriminate, convert and readout data in an autonomous mode. The digital part manages each channel independently thanks to 4 modules: top manager, acquisition, conversion and readout. Acquisition is in charge to manage the SCA with a depth of 2 for charge and fine time measurement. Coarse time measurement is made with a 24 bits gray counter. Readout module sends converted data of hit channels to an external system. Top manager controls the start and stop of the 3 others modules. The ASIC was submitted in June 2008.

PMm2: R&D on triggerless acquisition for next generation neutrino experiments

The next generation of proton decay and neutrino experiments, the post-SuperKamiokande detectors, such as those that will take place in megaton size water tanks, will require very large surfaces of photo-detection and will produce a large volume of data. Even with large hemispherical photomultiplier tubes (PMTs), the expected number of channels should reach hundreds of thousands. An ANR funded R&D program to implement a solution is presented here. The very large surface of photo-detection is segmented in macro pixels consisting of an array (2 × 2 m2) of 16 hemispherical 12-inch PMTs connected to autonomous underwater front-end electronics working in a triggerless data acquisition mode. The array is powered by a common high voltage and only one data cable allows the connection by network to the surface controller. This architecture allows a considerable reduction of the cost and facilitates the industrialization. This paper presents the complete architecture of the prototype system and tests results with 16 8-inch PMTs, validating the whole electronics, the built-in gain adjustment and the calibration principle.

The CpFM, an in-vacuum Cherenkov beam monitor for UA9 at SPS

The use of bent crystals for beam manipulation in particle accelerators is a well-assessed concept rapidly evolving into practical application. The experiments of the UA9 collaboration at the CERN-SPS have played a key role for a quantitative understanding of channeling and volume reflection mechanisms. Investigation of the channeling process close to a circulating beam ideally requires in vacuum detectors resolving the single particle, which should be located inside the vacuum pipe itself. Cherenkov radiators are potential candidates for such functionality due the reduced electro-magnetic interaction of the radiator material with the circulating charges and their compatibility with vacuum requirements in the beam pipe. For this purpose, we developed a device called Cherenkov detector for proton Flux Measurement (CpFM) that aims at counting the number of deflected protons of the beam halo surrounding the circulating beam with an accuracy of 15%. After a detailed description of the detection chain and its simulation, we present results of beam tests of different configurations, the calibration of the final device and the results of its first operation in the SPS.

Performance of CATIROC: ASIC for smart readout of large photomultiplier arrays

CATIROC (Charge And Time Integrated Read Out Chip) is a complete read-out chip manufactured in AustriaMicroSystem (AMS) SiGe 0.35 μm technology, designed to read arrays of 16 photomultipliers (PMTs). It is an upgraded version of PARISROC2 [1] designed in 2010 in the context of the PMm2 (square meter PhotoMultiplier) project [2]. CATIROC is a SoC (System on Chip) that processes analog signals up to the digitization and sparsification to reduce the cost and cable number. The ASIC is composed of 16 independent channels that work in triggerless mode, auto-triggering on the single photo-electron. It provides a charge measurement up to 400 photoelectrons (70 pC) on two scales of 10 bits and a timing information with an accuracy of 200 ps rms. The ASIC was sent for fabrication in February 2015 and then received in September 2015. It is a good candidate for two Chinese projects (LHAASO and JUNO). The architecture and the measurements will be detailed in the paper.

SPIROC: Design and performance of a dedicated very front-end for an ILC prototype Hadronic Calorimeter with SiPM

The SPIROC chip is a dedicated very front-end electronics to read out a prototype of the Analog Hadronic Calorimeter equipped with Silicon Photomultiplier (SiPM) for ILC (International Linear Collider). A first prototype of SPIROC has been fabricated in 2007 and a second version in 2010. Many test bench and test beam measurements have been performed showing a good overall behavior. However some limitations have been encountered. Another version has been submitted in February 2012 to correct these limitations and to improve the ASIC performances. After an exhaustive description of the ASIC, the performances will be presented in this paper.