Giuseppe Ascia

Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip

Efficient and deadlock-free routing is critical to the performance of networks-on-chip. The effectiveness of any adaptive routing algorithm strongly depends on the underlying selection strategy. A selection function is used to select the output channel where the packet will be forwarded on. In this paper we present a novel selection strategy that can be coupled with any adaptive routing algorithm. The proposed selection strategy is based on the concept of Neighbors-on-Path the aims of which is to exploit the situations of indecision occurring when the routing function returns several admissible output channels. The overall objective is to choose the channel that will allow the packet to be routed to its destination along a path that is as free as possible of congested nodes. Performance evaluation is carried out by using a flit-accurate simulator under traffic scenarios generated by both synthetic and real applications. Results obtained show how the proposed selection strategy applied to the Odd-Even routing algorithm yields an improvement in both average delay and saturation point up to 20% and 30% on average respectively, with a minimal overhead in terms of area occupation. In addition, a positive effect on total energy consumption is also observed under near-congestion packet injection rates.

Efficient design space exploration for application specific systems-on-a-chip

A reduction in the time-to-market has led to widespread use of pre-designed parametric architectural solutions known as system-on-a-chip (SoC) platforms. A system designer has to configure the platform in such a way as to optimize it for the execution of a specific application. Very frequently, however, the space of possible configurations that can be mapped onto a SoC platform is huge and the computational effort needed to evaluate a single system configuration can be very costly. In this paper we propose an approach which tackles the problem of design space exploration (DSE) in both of the fronts of the reduction of the number of system configurations to be simulated and the reduction of the time required to evaluate (i.e., simulate) a system configuration. More precisely, we propose the use of Multi-objective Evolutionary Algorithms as optimization technique and Fuzzy Systems for the estimation of the performance indexes to be optimized. The proposed approach is applied on a highly parameterized SoC platform based on a parameterized VLIW processor and a parameterized memory hierarchy for the optimization of performance and power dissipation. The approach is evaluated in terms of both accuracy and efficiency and compared with several established DSE approaches. The results obtained for a set of multimedia applications show an improvement in both accuracy and exploration time.

VLSI hardware architecture for complex fuzzy systems

This paper presents the design of a VLSI fuzzy processor, which is capable of dealing with complex fuzzy inference systems, i.e., fuzzy inferences that include rule chaining. The architecture of the processor is based on a computational model whose main features are: the capability to cope effectively with complex fuzzy inference systems; a detection phase of the rule with a positive degree of activation to reduce the number of rules to be processed per inference; parallel computation of the degree of activation of active rules; and representation of membership functions based on /spl alpha/-level sets. As the fuzzy inference can be divided into different processing phases, the processor is made up of a number of stages which are pipelined. In each stage several inference processing phases are performed parallelly. Its performance is in the order of 2 MFLIPS with 256 rules, eight inputs, two chained variables, and four outputs and 5.2 MFLIPS with 32 rules, three inputs, and one output with a clock frequency of 66 MHz.

Data Encoding Schemes in Networks on Chip

An ever more significant fraction of the overall power dissipation of a network-on-chip (NoC) based system-on-chip (SoC) is due to the interconnection system. In fact, as technology shrinks, the power contribute of NoC links starts to compete with that of NoC routers. In this paper, we propose the use of data encoding techniques as a viable way to reduce both power dissipation and energy consumption of NoC links. The proposed encoding scheme exploits the wormhole switching techniques and works on an end-to-end basis. That is, flits are encoded by the network interface (NI) before they are injected in the network and are decoded by the destination NI. This makes the scheme transparent to the underlying network since the encoder and decoder logic is integrated in the NI and no modification of the routers architecture is required. We assess the proposed encoding scheme on a set of representative data streams (both synthetic and extracted from real applications) showing that it is possible to reduce the power contribution of both the self-switching activity and the coupling switching activity in inter-routers links. As results, we obtain a reduction in total power dissipation and energy consumption up to 37% and 18%, respectively, without any significant degradation in terms of both performance and silicon area.

Neighbors-on-Path: A New Selection Strategy for On-Chip Networks

Efficient and deadlock-free routing is critical to the performance of networks-on-chip. In this paper we present an approach that can be coupled to any adaptive routing algorithm to improve the performance with a minimal overhead on area and energy consumption. The proposed approach introduces the concept of neighbors-on-path to exploit the situations of indecision occurring when the routing function returns several admissible output channels. A selection strategy is developed with the aim to choose the channel that will allow the packet to be routed to its destination along a path that is as free as possible of congested nodes. Performance evaluation is carried out by using a flit-accurate simulator on traffic scenarios generated by both synthetic and real applications. Results obtained show how the proposed selection policy applied to the odd-even routing algorithm outperforms other deterministic and adaptive routing algorithms both in average delay and energy consumption

A multiobjective genetic approach for system-level exploration in parameterized systems-on-a-chip

This paper deals with a significant problem affecting embedded system design methods based on parameterized systems on a chip (SOCs). It proposes a strategy for exploration of the configuration space of a parameterized SOC architecture to determine an accurate approximation of the power/performance Pareto-front. The strategy is based on genetic algorithms and is thoroughly evaluated in terms of accuracy, efficiency, and scalability using SOC platforms that differ as regards both architectural model and complexity. The results obtained show that the proposed approach gives an excellent approximation of the Pareto-optimal front in very short exploration times (up to two orders of magnitude shorter than those required by one of the best known and widely referenced approaches in the literature). In addition, our approach possesses a good degree of scalability as performance levels are maintained even when the architectural complexity increases.

Performance evaluation of efficient multi-objective evolutionary algorithms for design space exploration of embedded computer systems

Multi-objective evolutionary algorithms (MOEAs) have received increasing interest in industry because they have proved to be powerful optimizers. Despite the great success achieved, however, MOEAs have also encountered many challenges in real-world applications. One of the main difficulties in applying MOEAs is the large number of fitness evaluations (objective calculations) that are often needed before an acceptable solution can be found. There are, in fact, several industrial situations in which fitness evaluations are computationally expensive and the time available is very short. In these applications efficient strategies to approximate the fitness function have to be adopted, looking for a trade-off between optimization performance and efficiency. This is the case in designing a complex embedded system, where it is necessary to define an optimal architecture in relation to certain performance indexes while respecting strict time-to-market constraints. This activity, known as design space exploration (DSE), is still a great challenge for the EDA (electronic design automation) community. One of the most important bottlenecks in the overall design flow of an embedded system is due to simulation. Simulation occurs at every phase of the design flow and is used to evaluate a system which is a candidate for implementation. In this paper we focus on system level design, proposing an extensive comparison of the state-of-the-art of MOEA approaches with an approach based on fuzzy approximation to speed up the evaluation of a candidate system configuration. The comparison is performed in a real case study: optimization of the performance and power dissipation of embedded architectures based on a Very Long Instruction Word (VLIW) microprocessor in a mobile multimedia application domain. The results of the comparison demonstrate that the fuzzy approach outperforms in terms of both performance and efficiency the state of the art in MOEA strategies applied to DSE of a parameterized embedded system.

Fuzzy decision making in embedded system design

The use of Application Specific Instruction-set Processors (ASIP) is a solution to the problem of increasing complexity in embedded systems design. One of the major challenges in ASIP design is Design Space Exploration (DSE), because of the heterogeneity of the objectives and parameters involved. Typically DSE is a multi- objective search problem, where performance, power, area, etc. are the different optimization criteria. The output of a DSE strategy is a set of candidate design solutions called a Pareto-optimal set. Choosing a solution for system implementation from the Pareto- optimal set can be a difficult task, generally because Pareto-optimal sets can be extremely large or even contain an infinite number of solutions. In this paper we propose a methodology to assist the decision-maker in analysis of the solutions to multi-objective problems. By means of fuzzy clustering techniques, it finds the reduced Pareto subset, which best represents all the Pareto solutions. This optimal subset will be used for further and more accurate (but slower) analysis. As a real application example we address the optimization of area, performance, and power of a VLIW-based embedded system.

A VLSI Parallel Architecture For Fuzzy Expert Systems

In this paper we present a VLSI fuzzy processor whose main features are a scalable parallel architecture, and the computation of fuzzy inferences based on the α-level set theory, both of which are important in the field of intensive fuzzy computing, as in fuzzy expert systems. A specific analysis is made in the paper, of techniques for the representation of fuzzy sets, in relation to the amount of area occupied and the forms they can assume. From this analysis a solution is extracted and then used for the processor presented in the paper. The architecture of the processor is chosen after the assessment of possible alternatives by analyzing an appropriate probabilistic model. The processor comprises a set of units which work parallelly and asynschronously to process the various rules. The structure is easy to scale up, as an increase in the number of processing units does not produce bottlenecks in performance. The performance obtainable is about 310 KFLIPS, with a clock frequency of 60 Mhz, 8 input variables, either crisp or fuzzy, and an 8-bit resolution.

An adaptive transmitting power technique for energy efficient mm-wave wireless NoCs

Several emerging techniques have been recently proposed for alleviating the communication latency and the energy consumption issues in multi/many-core architectures. One of such emerging communication techniques, namely, WiNoC replaces the traditional wired links with the use of wireless medium. Unfortunately, the energy consumed by the RF transceiver (i.e., the main building block of a WiNoC), and in particular by its transmitter, accounts for a significant fraction of the overall communication energy. In this paper we propose a runtime tunable transmitting power technique for improving the energy efficiency of the transceiver in wireless NoC architectures. The basic idea is tuning the transmitting power based on the location of the recipient of the current communication. The integration of the proposed technique into two known WiNoC architectures, namely, iWise64 and McWiNoC resulted in an energy reduction of 43% and 60%, respectively.