Vincenzo Catania

Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip

Efficient and deadlock-free routing is critical to the performance of networks-on-chip. The effectiveness of any adaptive routing algorithm strongly depends on the underlying selection strategy. A selection function is used to select the output channel where the packet will be forwarded on. In this paper we present a novel selection strategy that can be coupled with any adaptive routing algorithm. The proposed selection strategy is based on the concept of Neighbors-on-Path the aims of which is to exploit the situations of indecision occurring when the routing function returns several admissible output channels. The overall objective is to choose the channel that will allow the packet to be routed to its destination along a path that is as free as possible of congested nodes. Performance evaluation is carried out by using a flit-accurate simulator under traffic scenarios generated by both synthetic and real applications. Results obtained show how the proposed selection strategy applied to the Odd-Even routing algorithm yields an improvement in both average delay and saturation point up to 20% and 30% on average respectively, with a minimal overhead in terms of area occupation. In addition, a positive effect on total energy consumption is also observed under near-congestion packet injection rates.

Application Specific Routing Algorithms for Networks on Chip

In this paper we present a methodology to develop efficient and deadlock free routing algorithms for Network-on-Chip (NoC) platforms which are specialized for an application or a set of concurrent applications. The proposed methodology, called application specific routing algorithm (APSRA), exploits the application specific information regarding pairs of cores which communicate and other pairs which never communicate in the NoC platform to maximize communication adaptivity and performance. The methodology also exploits the known information regarding concurrency/non-concurrency of communication transactions among cores for the same purpose. We demonstrate, through analysis of adaptivity as well as simulation based evaluation of latency and throughput, that algorithms produced by the proposed methodology give significantly higher performance as compared to other deadlock free algorithms for both homogeneous as well as heterogeneous 2D mesh topology NoC systems. For example, for homogeneous mesh NoC, APSRA results in approximately 30% less average delay as compared to odd-even algorithm just below saturation load. Similarly the saturation load point for APSRA is significantly higher as compared to other adaptive routing algorithms for both homogeneous and non-homogeneous mesh networks.

Efficient design space exploration for application specific systems-on-a-chip

A reduction in the time-to-market has led to widespread use of pre-designed parametric architectural solutions known as system-on-a-chip (SoC) platforms. A system designer has to configure the platform in such a way as to optimize it for the execution of a specific application. Very frequently, however, the space of possible configurations that can be mapped onto a SoC platform is huge and the computational effort needed to evaluate a single system configuration can be very costly. In this paper we propose an approach which tackles the problem of design space exploration (DSE) in both of the fronts of the reduction of the number of system configurations to be simulated and the reduction of the time required to evaluate (i.e., simulate) a system configuration. More precisely, we propose the use of Multi-objective Evolutionary Algorithms as optimization technique and Fuzzy Systems for the estimation of the performance indexes to be optimized. The proposed approach is applied on a highly parameterized SoC platform based on a parameterized VLIW processor and a parameterized memory hierarchy for the optimization of performance and power dissipation. The approach is evaluated in terms of both accuracy and efficiency and compared with several established DSE approaches. The results obtained for a set of multimedia applications show an improvement in both accuracy and exploration time.

A methodology for design of application specific deadlock-free routing algorithms for NoC systems

In this paper, we present a methodology to specialize the routing algorithm in routing table based NoC routers. It tries to maximize the communication performance while ensuring deadlock free routing for an application. We demonstrate through analysis that routing algorithms generated by our methodology have higher adaptiveness as compared to turn-model based deadlock free routing algorithms for a mesh topology NoC architecture. Performance evaluation is carried out by using a flit-accurate simulator on traffic scenarios generated by both synthetic and real applications. The routing algorithms generated by the proposed methodology achieve an improvement in delay close to 50% and 30% over deterministic XY routing algorithm and adaptive odd-even routing algorithm respectively.

A comparative analysis of fuzzy versus conventional policing mechanisms for ATM networks

In ATM networks, usage parameter control is required in order to ensure that each source conforms to its negotiated parameters. To this purpose, several policing methods, such as leaky bucket and window mechanisms, have been introduced in literature. However, traditional methods have proved to be inefficient in coping with the conflicting requirements of ideal policing, that is, a low false alarm probability and high responsiveness. This led us to explore alternative solutions based on artificial intelligence techniques, specifically, in the field of fuzzy systems. We propose a policing mechanism based on fuzzy logic that aims at detecting violations of the parameters negotiated. The main characteristics of the proposed fuzzy policer are simplicity and the capacity to combine a high degree of responsiveness with a selectivity close to that of an ideal policer. Moreover, it can easily be implemented in hardware, thus, enhancing both cost and processing performance. The reported simulation results show that the performance of our fuzzy policer is much better than that of conventional policing mechanisms.

Noxim: An open, extensible and cycle-accurate network on chip simulator

Emerging on-chip communication technologies like wireless Networks-on-Chip (WiNoCs) have been proposed as candidate solutions for addressing the scalability limitations of conventional multi-hop NoC architectures. In a WiNoC, a subset of network nodes are equipped with a wireless interface which allows them long-range communication in a single hop. This paper presents Noxim, an open, configurable, extendible, cycle-accurate NoC simulator developed in SystemC which allows to analyze the performance and power figures of both conventional wired NoC and emerging WiNoC architectures.

VLSI hardware architecture for complex fuzzy systems

This paper presents the design of a VLSI fuzzy processor, which is capable of dealing with complex fuzzy inference systems, i.e., fuzzy inferences that include rule chaining. The architecture of the processor is based on a computational model whose main features are: the capability to cope effectively with complex fuzzy inference systems; a detection phase of the rule with a positive degree of activation to reduce the number of rules to be processed per inference; parallel computation of the degree of activation of active rules; and representation of membership functions based on /spl alpha/-level sets. As the fuzzy inference can be divided into different processing phases, the processor is made up of a number of stages which are pipelined. In each stage several inference processing phases are performed parallelly. Its performance is in the order of 2 MFLIPS with 256 rules, eight inputs, two chained variables, and four outputs and 5.2 MFLIPS with 32 rules, three inputs, and one output with a clock frequency of 66 MHz.

Data Encoding Schemes in Networks on Chip

An ever more significant fraction of the overall power dissipation of a network-on-chip (NoC) based system-on-chip (SoC) is due to the interconnection system. In fact, as technology shrinks, the power contribute of NoC links starts to compete with that of NoC routers. In this paper, we propose the use of data encoding techniques as a viable way to reduce both power dissipation and energy consumption of NoC links. The proposed encoding scheme exploits the wormhole switching techniques and works on an end-to-end basis. That is, flits are encoded by the network interface (NI) before they are injected in the network and are decoded by the destination NI. This makes the scheme transparent to the underlying network since the encoder and decoder logic is integrated in the NI and no modification of the routers architecture is required. We assess the proposed encoding scheme on a set of representative data streams (both synthetic and extracted from real applications) showing that it is possible to reduce the power contribution of both the self-switching activity and the coupling switching activity in inter-routers links. As results, we obtain a reduction in total power dissipation and energy consumption up to 37% and 18%, respectively, without any significant degradation in terms of both performance and silicon area.

Neighbors-on-Path: A New Selection Strategy for On-Chip Networks

Efficient and deadlock-free routing is critical to the performance of networks-on-chip. In this paper we present an approach that can be coupled to any adaptive routing algorithm to improve the performance with a minimal overhead on area and energy consumption. The proposed approach introduces the concept of neighbors-on-path to exploit the situations of indecision occurring when the routing function returns several admissible output channels. A selection strategy is developed with the aim to choose the channel that will allow the packet to be routed to its destination along a path that is as free as possible of congested nodes. Performance evaluation is carried out by using a flit-accurate simulator on traffic scenarios generated by both synthetic and real applications. Results obtained show how the proposed selection policy applied to the odd-even routing algorithm outperforms other deterministic and adaptive routing algorithms both in average delay and energy consumption

Using fuzzy logic in ATM source traffic control: lessons and perspectives

Due to its capacity to capture human expertise and to formalize approximate reasoning processes, fuzzy logic can be a good answer to the many challenges of congestion control in ATM networks. The authors deal with the application of fuzzy logic to problems of usage parameter control and propose a simple mechanism which, avoiding complex mathematical calculations, guarantees low response times while remaining effective. The flexibility of the fuzzy control proposed is discussed with respect to the probability of facing various types of traffic sources, ranging from bursty to MPEG video.