Andrea Mineo

Noxim: An open, extensible and cycle-accurate network on chip simulator

Emerging on-chip communication technologies like wireless Networks-on-Chip (WiNoCs) have been proposed as candidate solutions for addressing the scalability limitations of conventional multi-hop NoC architectures. In a WiNoC, a subset of network nodes are equipped with a wireless interface which allows them long-range communication in a single hop. This paper presents Noxim, an open, configurable, extendible, cycle-accurate NoC simulator developed in SystemC which allows to analyze the performance and power figures of both conventional wired NoC and emerging WiNoC architectures.

Cycle-Accurate Network on Chip Simulation with Noxim

The on-chip communication in current Chip-MultiProcessors (CMP) and MultiProcessor-SoC (MPSoC) is mainly based on the Network-on-Chip (NoC) design paradigm. Unfortunately, it is foreseen that conventional NoC architectures cannot sustain the performance, power, and reliability requirements demanded by the next generation of manycore architectures. Recently, emerging on-chip communication technologies, like wireless Networks-on-Chip (WiNoCs), have been proposed as candidate solutions for addressing the scalability limitations of conventional multi-hop NoC architectures. In a WiNoC, a subset of network nodes are equipped with a wireless interface which allows them long-range communication in a single hop. Assessing the performance and power figures of NoC and WiNoC architectures requires the availability of simulation tools that are often limited on modeling specific network configurations. This article presents Noxim, an open, configurable, extendible, cycle-accurate NoC simulator developed in SystemC, which allows to analyze the performance and power figures of both conventional wired NoC and emerging WiNoC architectures.

An adaptive transmitting power technique for energy efficient mm-wave wireless NoCs

Several emerging techniques have been recently proposed for alleviating the communication latency and the energy consumption issues in multi/many-core architectures. One of such emerging communication techniques, namely, WiNoC replaces the traditional wired links with the use of wireless medium. Unfortunately, the energy consumed by the RF transceiver (i.e., the main building block of a WiNoC), and in particular by its transmitter, accounts for a significant fraction of the overall communication energy. In this paper we propose a runtime tunable transmitting power technique for improving the energy efficiency of the transceiver in wireless NoC architectures. The basic idea is tuning the transmitting power based on the location of the recipient of the current communication. The integration of the proposed technique into two known WiNoC architectures, namely, iWise64 and McWiNoC resulted in an energy reduction of 43% and 60%, respectively.

Runtime Tunable Transmitting Power Technique in mm-Wave WiNoC Architectures

Emerging on-chip communication technologies, like wireless networks-on-chip (WiNoCs), have been recently proposed as candidate solutions for addressing the scalability limitations of conventional multihop network on chip (NoC) architectures. In a WiNoC, a subset of network nodes, namely, radio hubs, are equipped with a wireless interface that allows them to wirelessly communicate with other radio hubs. Thus, long-range communications, which would involve multiple hops in a conventional wireline NoC, can be realized by a single hop through the radio medium. Unfortunately, the energy consumed by the RF transceiver into the radio hub (i.e., the main building block in a WiNoC), and in particular by its transmitter, accounts for a significant fraction of the overall communication energy. In order to alleviate such contribution, this paper presents a runtime tunable transmitting power technique for improving the energy efficiency of the transceiver in WiNoC architectures. The basic idea is tuning the transmitting power based on the physical location of the recipient of the current communication. Specifically, based on the destination address of the incoming packet, the radio hub tunes its transmitting power to a minimum level, but high enough to reach the destination antenna without exceeding a certain bit error ratio. The proposed technique is general and can be applied to any WiNoC architecture. Its application on different representative WiNoC architectures results in an average energy reduction up to 50% without any impact on performance and with a negligible overhead in terms of silicon area.

Exploiting antenna directivity in wireless NoC architectures

Wireless Network-on-Chip (WiNoC) is an emerging on-chip communication paradigm and a candidate solution for dealing with the scalability problems which affect current and next generation many-core architectures. In a WiNoC, the transceivers that allow the conversion between electrical and radio signals, account for a significant fraction of the total communication energy budget. In particular, the transmitting power for wireless communications is strongly affected by the orientation of the antennas. This paper studies the impact of antennas orientation on energy figures of a WiNoC architecture and performs a design space exploration for determining the optimal orientation of the antennas in such a way to minimize the communication energy consumption. Experiments have been carried out on state-of-the-art WiNoC topologies, on both synthetic and real traffic scenarios, and validated by means of a commercial field solver simulator. When the antennas are optimally oriented, up to 80% energy saving (as compared to the case in which antennas have all the same orientation) has been observed.

A closed loop transmitting power self-calibration scheme for energy efficient WiNoC architectures

In a wireless Network-on-Chip (WiNoC) the radio transceiver accounts for a significant fraction of the total communication energy. Recently, a configurable transceiver architecture able to regulate its transmitting power based on the location of the destination node has been proposed. Unfortunately, the use of such transceiver requires a costly, time consuming and complex characterization phase performed at design time and mainly based on the use of field solver simulators whose accuracy has not yet been proved in the context of integrated on-chip antennas. In this paper we present a closed loop transmitting power self-calibration mechanism which allows to determine on-line the optimal transmitting power for each transmitting and receiving pair in a WiNoC. The proposed mechanism is general and can be applied to any WiNoC architecture with a low overhead in terms of silicon area. Its application to three well known WiNoC architectures shows its effectiveness in drastically reducing the overall communication energy (up to 50%) with a limited impact on performance.

Energy efficient transceiver in wireless Network on Chip architectures

The emergent wireless Network-on-Chip (WiNoC) design paradigm has been proposed as a viable solution for addressing the scalability issues affecting the on-chip communication system in future manycores architectures. Within this scenario, the energy contribution of the buffers (both of the routers and radio-hubs) and the transceivers of the radio-hubs, account for a significant fraction of the total communication energy budget. In this paper, we propose a novel energy management scheme aimed at improving the energy efficiency of a WiNoC architecture based on the selective disabling of the power hungry modules that are predicted being not used during the forthcoming clock cycles. The proposed scheme, applied on different WiNoC topologies with different configurations and under different traffic scenarios, has shown interesting energy saving without any impact on the performance metrics and with a negligible impact on silicon area.

NoC links energy reduction through link voltage scaling

The power dissipated by the links of a network-on-chip (NoC) accounts for a significant fraction of the overall power dissipated by the on-chip communication fabric. Such fraction becomes more relevant as technology shrinks. This paper presents a technique aimed at reducing the energy consumption of the NoC by means of link voltage swing reduction. The basic idea is run-time varying the link voltage swing based on the communication requirements in terms of reliability. Specifically, the voltage swing of the link is reduced when it has to transmit the flits of a packet belonging to a communication which admits a bit error rate higher than the usual. The experiments carried out on both synthetic and real traffic patterns show the effectiveness of the proposed technique which allows to save more than 20% of energy depending on the communications reliability requirements.

Improving Energy Efficiency in Wireless Network-on-Chip Architectures

Wireless Network-on-Chip (WiNoC) represents a promising emerging communication technology for addressing the scalability limitations of future manycore architectures. In a WiNoC, high-latency and power-hungry long-range multi-hop communications can be realized by performance- and energy-efficient single-hop wireless communications. However, the energy contribution of such wireless communication accounts for a significant fraction of the overall communication energy budget. This article presents a novel energy managing technique for WiNoC architectures aimed at improving the energy efficiency of the main elements of the wireless infrastructure, namely, radio-hubs. The rationale behind the proposed technique is based on selectively turning off, for the appropriate number of cycles, all the radio-hubs that are not involved in the current wireless communication. The proposed energy managing technique is assessed on several network configurations under different traffic scenarios both synthetic and extracted from the execution of real applications. The obtained results show that the application of the proposed technique allows up to 25% total communication energy saving without any impact on performance and with a negligible impact on the silicon area of the radio-hub.

On-Chip Communication Energy Reduction Through Reliability Aware Adaptive Voltage Swing Scaling

In a multi/many-core system, the network-on-chip (NoC)-based communication backbone is responsible for a relevant fraction of the overall energy budget. Reducing the voltage swing for signaling in crossbars and links results in significant energy saving. Unfortunately, as voltage swing reduces, the bit error rate increases, that in turn compromises the communication reliability. Starting from the assumption that not all the communications need same level of reliability, in this paper we propose techniques and architectures for run-time tuning of the voltage swing of the crossbars and interrouter links. The proposed technique is compared with the state of the art in link energy reduction through data encoding under both synthetic and real traffic scenarios. We found that the proposed techniques allow to significantly reduce the energy consumption of the NoC fabric without degrading the performance metrics. Energy savings ranging from 20% to 43% have been observed without any relevant impact on the performance metrics.