Giuseppe Di Guglielmo

HIFsuite: tools for HDL code conversion and manipulation

HIFSuite ia a set of tools and application programming interfaces (APIs) that provide support for modeling and verification of HW/SW systems. The core of HIFSuite is the HDL Intermediate Format (HIF) language upon which a set of front-end and back-end tools have been developed to allow the conversion of HDL code into HIF code and vice versa. HIFSuite allows designers to manipulate and integrate heterogeneous components implemented by using different hardware description languages (HDLs). Moreover, HIFSuite includes tools, which rely on HIF APIs, for manipulating HIF descriptions in order to support code abstraction/refinement and postrefinement verification.

An Analysis of Accelerator Coupling in Heterogeneous Architectures

Existing research on accelerators has emphasized the performance and energy efficiency improvements they can provide, devoting little attention to practical issues such as accelerator invocation and interaction with other on-chip components (e.g. cores, caches). In this paper we present a quantitative study that considers these aspects by implementing seven high-throughput accelerators following three design models: tight coupling behind a CPU, loose out-of-core coupling with Direct Memory Access (DMA) to the LLC, and loose out-of-core coupling with DMA to DRAM. A salient conclusion of our study is that working sets of non-trivial size are best served by loosely-coupled accelerators that integrate private memory blocks tailored to their needs.

HIFSuite: Tools for HDL code conversion and manipulation

HIFSuite ia a set of tools and application programming interfaces (APIs) that provide support for modeling and verification of HW/SW systems. The core of HIFSuite is the HDL Intermediate Format (HIF) language upon which a set of front-end and back-end tools have been developed to allow the conversion of HDL code into HIF code and vice versa. HIFSuite allows designers to manipulate and integrate heterogeneous components implemented by using different hardware description languages (HDLs). Moreover, HIFSuite includes tools, which rely on HIF APIs, for manipulating HIF descriptions in order to support code abstraction/refinement and post-refinement verification.

Model-driven design and validation of embedded software

This paper presents a model-based framework for designing and validating embedded software (ESW). The design infrastructure is a rapid-application-development suite for ESW, i.e., radCASE, which provides the user with an off the shelf designing environment based on model-driven paradigm. The validation infrastructure, i.e., radCHECK, is based on Property Editor. Such an editor simplifies the definition of PSL properties by exploiting PSL-based templates, that can be automatically compiled into executable checkers by using the integrated Checker Generator engine. Besides, radCHECK comprises a testcase generation infrastructure, i.e., Ulisse, which is based on an corner-case-oriented concolic approach for ESW, thus it is able to simulate the ESW and the checkers by using high-coverage testcases.

On the integration of model-driven design and dynamic assertion-based verification for embedded software

Model-driven design (MDD) aims at elevating design to a higher level of abstraction than that provided by third-generation programming languages. Concurrently, assertion-based verification (ABV) relies on the definition of temporal assertions to enhance functional verification targeting the correctness of the design execution with respect to the expected behavior. Both MDD and ABV have affirmed as effective methodologies for design and verification of HW components of embedded systems. Nonetheless, MDD and ABV individually suffer some limitations that prevent their integration in the embedded-software (ESW) design and verification flow. In particular, MDD requires the integration of an effective methodology for monitoring specification conformance, and dynamic ABV relies on simulation assumptions, satisfied in the HW domain, but which cannot be straightforward guaranteed during the execution of ESW. In this work, we present a suitable combination of MDD and dynamic ABV as an effective solution for ESW design and verification. A suite composed of two off-the-shelf tools has been developed for supporting this integrated approach. The MDD tool, i.e., radCASE, is a rapid-application-development environment for ESW that provides the user with a comprehensive approach to cover the complete modeling and synthesis process of ESW. The dynamic ABV environment, i.e., radCHECK, integrates computer-aided and template-based assertion definition, automatic checker generation, and effective stimuli generation, making dynamic ABV really practical to check the correctness of the radCASE outcome.

RTOS-aware refinement for TLM2.0-based HW/SW designs

Refinement of untimed TLM models into a timed HW/SW platform is a step by step design process which is a trade-off between timing accuracy of the used models and correct estimation of the final timing performance. The use of an RTOS on the target platform is mandatory in the case real-time properties must be guaranteed. Thus, the question is when the RTOS must be introduced in this step by step refinement process. This paper proposes a four-level RTOS-aware refinement methodology that, starting from an untimed TLMSystemC description of the whole system, progressively introduce HW/SW partitioning, timing, device driver and RTOS functionalities, till to obtain an accurate model of the final platform, where SW tasks run upon an RTOS hosted by QEMU and HW components are modeled by cycle accurate TLM descriptions. Each refinement level allows the designer to estimate more and more accurate timing properties, thus anticipating design decisions without being constrained to leave timing analysis to the final step of the refinement. The effectiveness of the methodology has been evaluated in the design of two complex platforms.

Efficient Generation of Stimuli for Functional Verification by Backjumping Across Extended FSMs

Extended finite state machines (EFSMs) can be efficiently adopted to model the functionality of complex designs without incurring the state explosion problem typical of the more traditional FSMs. However, traversing an EFSM can be more difficult than an FSM because the guards of EFSM transitions involve both primary inputs and registers. This paper first analyzes the hardness of traversing an EFSM according to the characteristics of its transitions. Then, it presents a methodology to generate an EFSM which is easy to be traversed. Finally, it proposes a functional deterministic automatic test pattern generation (ATPG) approach that exploits such EFSMs for functional verification. In particular, the ATPG approach joins backjumping, learning, and constraint solving to (i) early identify possible symptoms of design errors by efficiently exploring the whole state space of the design under verification (DUV), and (ii) generate effective input sequences to be used in further verification steps which require to stimulate the DUV. The effectiveness of the proposed approach is confirmed in the experimental result section, where it is compared with both genetic and pseudo-deterministic techniques.

Semi-formal functional verification by EFSM traversing via NuSMV

Simulation-based verification of hardware systems is well-established in industrial practice thanks to the ease-of-use of the approach and to its scalability. However, it notoriously suffers from the lack of exhaustiveness. On the other hand, while pure formal verification techniques provide high confidence in the design correctness, they are very limited in terms of scalability. As an alternative, semi-formal validation techniques are currently under investigation. Semi-formal approaches fulfil the tradeoff between high-coverage results, scalability of the design, and reduced resource requirements. In this work, a semi-formal approach for hardware verification is presented by exploiting constrained random simulation and extended finite state machine (EFSM) traversal through heuristics. The proposed heuristics aim to uniformly, and rapidly, visit the design space, exploiting a NuSMV-based constraint solving technique to efficiently cover corner cases. In this context, a constraint solving interface has been built on top of the NuSMV model checker. We present experimental results comparing the proposed heuristics with existent approaches, and the effectiveness of our NuSMV-based strategy with respect to the adoption of a state of the art constraint solver (ECLiPSe).

Dynamic property mining for embedded software

The importance of specification definition in the embedded-software design flow has been proven over the years. The entire design process relies on the specification quality, which inevitably depends on designer knowledge and skills. Automatic property mining is part of the efforts proposed to make this activity easier for the designers. Nonetheless, the existing approaches are limited to the detection of either arithmetic invariants of programs or temporal properties for Boolean designs, e.g., bit-level hardware descriptions. In this work, we present a dynamic mining approach able to infer linear temporal logic (LTL) properties for embedded software. The mined properties are in the form of temporal relationships between arithmetic expressions. The approach considers the execution traces only, thus it is completely independent from the code implementation. Experimental results demonstrate the effectiveness of the approach.

System-level memory optimization for high-level synthesis of component-based SoCs

The design of specialized accelerators is essential to the success of many modern Systems-on-Chip. Electronic system-level design methodologies and high-level synthesis tools are critical for the efficient design and optimization of an accelerator. Still, these methodologies and tools offer only limited support for the optimization of the memory structures, which are often responsible for most of the area occupied by an accelerator. To address these limitations, we present a novel methodology to automatically derive the memory sub-systems of SoC accelerators. Our approach enables compositional design-space exploration and promotes design reuse of the accelerator specifications. We illustrate its effectiveness by presenting experimental results on the design of two accelerators for a high-performance embedded application.