Cristina Marconcini

Model-driven design and validation of embedded software

This paper presents a model-based framework for designing and validating embedded software (ESW). The design infrastructure is a rapid-application-development suite for ESW, i.e., radCASE, which provides the user with an off the shelf designing environment based on model-driven paradigm. The validation infrastructure, i.e., radCHECK, is based on Property Editor. Such an editor simplifies the definition of PSL properties by exploiting PSL-based templates, that can be automatically compiled into executable checkers by using the integrated Checker Generator engine. Besides, radCHECK comprises a testcase generation infrastructure, i.e., Ulisse, which is based on an corner-case-oriented concolic approach for ESW, thus it is able to simulate the ESW and the checkers by using high-coverage testcases.

On the integration of model-driven design and dynamic assertion-based verification for embedded software

Model-driven design (MDD) aims at elevating design to a higher level of abstraction than that provided by third-generation programming languages. Concurrently, assertion-based verification (ABV) relies on the definition of temporal assertions to enhance functional verification targeting the correctness of the design execution with respect to the expected behavior. Both MDD and ABV have affirmed as effective methodologies for design and verification of HW components of embedded systems. Nonetheless, MDD and ABV individually suffer some limitations that prevent their integration in the embedded-software (ESW) design and verification flow. In particular, MDD requires the integration of an effective methodology for monitoring specification conformance, and dynamic ABV relies on simulation assumptions, satisfied in the HW domain, but which cannot be straightforward guaranteed during the execution of ESW. In this work, we present a suitable combination of MDD and dynamic ABV as an effective solution for ESW design and verification. A suite composed of two off-the-shelf tools has been developed for supporting this integrated approach. The MDD tool, i.e., radCASE, is a rapid-application-development environment for ESW that provides the user with a comprehensive approach to cover the complete modeling and synthesis process of ESW. The dynamic ABV environment, i.e., radCHECK, integrates computer-aided and template-based assertion definition, automatic checker generation, and effective stimuli generation, making dynamic ABV really practical to check the correctness of the radCASE outcome.

Logic-level mapping of high-level faults

Many high-level fault models have been proposed in the past to perform verification at functional level, however high-level automatic test pattern generators (ATPGs) are still in a prototyping phase, while very efficient logic-level ATPGs are available.On the other side, coverage metrics and functional fault models are used to guide the generation of functional tests achieving high fault coverage in a relatively short time with respect to traditional gate-level ATPGs. However, what is the effectiveness of test sequences generated at functional level with respect to the more traditional gate-level stuck-at fault model?The paper presents an accurate analysis of the correlation between high-level fault models and the gate-level stuck-at fault model and it proposes a strategy to map high-level faults into logic-level faults. Thus, functional verification, based on a high-level fault model, can be performed by exploiting the capability of state of the art logic-level ATPGs. Experimental results highlight the effectiveness of the methodology.

Improving gate-level ATPG by traversing concurrent EFSMs

The paper describes a high-level pseudodeterministic ATPG that explores the DUT state space by exploiting an easy-to-traverse extended FSM model. Testing of hard-to-detect faults is thus improved. Generated test sequences are very effective in detecting both high-level faults and gate-level stuck-at faults. Thus, the reuse of test sequences generated by the proposed ATPG allows to improve the stuck-at fault coverage and to reduce the execution time of commercial gate-level ATPGs.

Improving high-level and gate-level testing with FATE: A functional automatic test pattern generator traversing unstabilised extended FSM

A functional automatic test pattern generator (ATPG) that explores the design under test (DUT) state space by exploiting an easy-to-traverse extended finite state machine (FSM) model has been described. The ATPG engine relies on learning, backjumping and constraint logic programming to deterministically generate test vectors for traversing all transitions of the extended FSM. Testing of hard-to-detect faults is thus improved. The generated test sequences are very effective in detecting both high-level faults and gate-level stuck-at faults. Thus, the reuse of test sequences generated by the proposed ATPG allows also to improve the stuck-at fault coverage and to reduce the execution time of commercial gate-level ATPGs.

EFSM Manipulation to Increase High-Level ATPG Effectiveness

The EFSM paradigm can be efficiently adopted to model complex designs without incurring in the state explosion problem typical of the traditional FSM paradigm. However, traversing an EFSM can be more difficult than an FSM because the guards of transitions involve both primary inputs and internal registers. Hard-to-traverse transitions represent a problem when a simulation-based approach is applied to perform functional validation. In fact, they do not allow a complete exploration of the state space. In this paper, EFSM hard-to-traverse transitions are classified, and a set of transformations is proposed to generate an EFSM model which is easy to be traversed. This allows pseudo-deterministic ATPGs to more uniformly analyze the state space of the resulting EFSM

FATE: a Functional ATPG to Traverse Unstabilized EFSMs

The paper describes a functional ATPG that explores the DUT state space by exploiting an easy-to-traverse extended FSM model. The ATPG engine relies on learning, backjumping and constraint logic programming to deterministically generate test vectors for traversing all transitions of the EFSM

Functional verification based on the EFSM model

The paper presents a methodology for addressing hard-to-detect faults when a high-level ATPG is applied to verify functional descriptions of sequential circuits. A particular kind of extended finite state machines is adopted to improve detectability of such faults.

Functional fault coverage: the chamber of secrets or an accurate estimation of gate-level coverage?

More and more functional verification is attracting EDA researchers and industrial companies interested in digital system validation. Coverage metrics and functional fault models are used to guide the generation of functional tests achieving high fault coverage in a relatively short time with respect to traditional gate-level ATPGs. However, what is the effectiveness of test sequences generated at functional level with respect to the more traditional gate-level stuck at fault model? The paper presents an accurate analysis of the correlation between the high-level bit coverage fault model and the gate-level stuck-at fault model.

Redundant functional faults reduction by saboteurs synthesis [logic verification]

High-level descriptions of digital systems are perturbed by using high-level fault models in order to perform functional verification. Fault lists should be accurately created in order to avoid waste of time during ATPG and fault simulation. However, automatic fault injection tools can insert redundant faults which are not symptoms of design errors. Such redundant faults should be removed from the fault list before starting the verification session. This paper proposes an automatic strategy for high-level faults injection, which removes redundant bit coverage faults. An efficient implementation of a bit coverage saboteur is proposed, which allows one to use synthesis for redundant faults removal. Experimental results highlight the effectiveness of the methodology. By using the proposed injection strategy, functional APTG time is reduced and fault coverage is increased.