Giuseppe Visalli

Bus-switch coding for reducing power dissipation in off-chip buses

We present a novel coding scheme for reducing bus power dissipation. The presented approach is well suited to driving off-chip buses, where the line capacitance is a dominant factor. A distinctive feature of the technique is the dynamic reordering of bus line positions, in order to minimize the toggling activity on physical bus wires. The effectiveness of the approach is demonstrated through cycle-accurate simulation of industrial benchmarks in conjunction with post-layout evaluation of speed, power and area overhead.

Analysis and Implementation of a Novel Leading Zero Anticipation Algorithm for Floating-Point Arithmetic Units

Leading zero anticipation with error correction is a widely adopted technique in the implementation of high-speed IEEE-754-compliant floating-point units (FPUs), which are critical for area and power in multimedia-oriented systems-on-chips. We investigated a novel LZA algorithm allowing us to remove error correction circuitry by reducing the error rate below a commonly accepted limit for image processing applications, which is not achieved by previous techniques. We embedded our technique into a complete FPU definitely obtaining both area saving and overall FPU latency reduction with respect to traditional designs.

Low-power floating-point encoding for signal processing applications

The IEEE defined a standard for floating-point arithmetic used by processing systems (ANSI/IEEE Std 754-1985). This directive encodes floating point numbers using a maximum of 64 bits: 23 bits of fractional in single precision format and 52 bits of fractional in double precision format. The new multimedia terminals require low-power applications; the most important floating-point units (adders and multipliers) represent a significant part of total power wasted by a modern system-on-chip. They might dissipate less power by using a reduced format representation. To verify this possibility, floating-point operations are simulated by real systems using different formats. We discuss multimedia systems operating in different scenarios, such as wireless communication and image manipulation.

Performance-timing overhead trade-off analysis for a low-power data bus encoding based on input lines reordering

This paper analyzes the performance and timing overhead trade-off for a recently proposed data bus encoding scheme for low-power based on data lines reordering. The bus switch (BS) mechanism introduces greater activity savings than previous approaches; the hardware complexity of the encoder suggests to apply BS in off-chip buses, where the parasitic capacitance makes dynamic power dissipation in the bus lines the dominant contribution to power consumption. In the basic BS implementation, the encoding circuits included extra bus lines which degrade the energy saving. This paper illustrates and analyzes a circuit implementation with only one extra line, at the cost of a small time overhead. This solution strongly enhances the advantage in off-chip communications, where the available number of pads represents a key resource in low-cost packages. Our results indicate that the effectiveness of the approach strongly depend on an a-priori traffic analysis.

Fuzzy Control of Coding Schemes for Reducing Energy Dissipation in Off-Chip Buses

In this paper, we proposed an high-speed and low-power off-chip data bus interface based on the best coding schemes in this hard operative condition. We analyzed the clustered bus invert method and the bus switch coding, a newly proposed approach based on bus lines logically re-ordered. We proposed an high speed and low-power bus interface based on the combined employment of these two approaches controlled by a 9-rules Takagi-Sugeno analog fuzzy controller. The controller analyzes the binary traffic statistical property changing on the fly the used coding scheme. The fuzzy controller has been designed taking care of total energy dissipation such to do not compromise the benefit of coding approaches. The controller is able also to re-configure the bus switch sub-section in an operative condition where original approach introduces strong power losses. We demonstrated the effectiveness of the approach designing at transistor level the analog fuzzy controller and the digital part of the bus interface. Simulation conducted with H-SPICE and NANOSIM confirmed the bus interface is the optimal trade-off for reducing dynamic energy in off-chip buses.

An Ultra-Low Power Data Aggregation System for Wireless Micro Sensor Networks

The paper introduced a novel methodology, for reducing energetic consumption, during data compression in homogenous sensor nodes organized in a cluster based network. Our approach employed a bit-wise operator previously used in the context of the reduction of dynamic energy in external buses. The document defined the compression and decompression laws based on this operator, in a conceptual way much similar to the code division multiple access (CDMA) systems, used in the telecommunication scenario. Each sensor has internally associated a digital signature, used in the compression stage. The host computer tries to recover the original waveform executing the cited operator and applying the inverse signature. The original data has been corrupted by an interference process, which depends on the presence of the other users in the same cluster. The host computer is able to select the best signatures, mostly reducing the energy of the interfering process. Simulations conducted with Matlab and SimplePower indicated our approach gains an 85% in energy consumption compared to the simpler algorithm up to now known (Least Mean Squares). Moreover, simulations verified the host has the capability to recover the transmitted waveforms in their fundamental harmonic members.

Encoding circuits for low power optical on-chip communications

The increased demands of high data-rate communications could be satisfied by optical semiconductor elements. Actually, these devices represent an important role in the total energy budget available for the chip. This work presents a low-power encoding technique which optimizes the statistical distribution so as to reduce the energy dissipated in optical communications. We evaluated the encoding circuits referring to 180 nm, 130 nm and 90 nm CMOS technologies. Our results show an up to 12% electrical current reduction in the on-chip light emitter.