Glenn E. R. Cowan

A VLSI analog computer/digital computer accelerator

The design of a single-chip VLSI analog computer fabricated in a 0.25-/spl mu/m CMOS process is described. It contains 80 integrators, 336 other linear and nonlinear analog functional blocks, switches for their interconnection, and circuitry to enable the systems programing and control. The IC is controlled, programmed and measured by a PC via a data acquisition card. This arrangement has been used to simulate ordinary differential equations (ODEs), partial differential equations, and stochastic differential equations with moderate accuracy, significantly faster than a modern workstation. Techniques for using the digital computer to refine the solution from the analog computer are presented. Solutions from the analog computer have been used to accelerate a digital computers solution of the periodic steady state of an ODE by more than 10/spl times/. The IC occupies 1 cm/sup 2/ and consumes 300 mW. An analysis has been done showing that the analog computer dissipates 0.02% to 1% of the energy of a general purpose digital microprocessor and about 2% to 20% of the energy of a digital signal processor, when solving the same differential equation.

Low-Swing Differential Conditional Capturing Flip-Flop for LC Resonant Clock Distribution Networks

In this paper we introduce a new flip-flop for use in a low- swing LC resonant clocking scheme. The proposed low-swing differential conditional capturing flip-flop (LS-DCCFF) operates with a low-swing sinusoidal clock through the utilization of reduced swing inverters at the clock port. The functionality of the proposed flip-flop was verified at extreme corners through simulations with parasitics extracted from layout. The LS-DCCFF enables 6.5% reduction in power compared to the full- swing flip-flop with 19% area overhead. In addition, a frequency dependent delay associated with driving pulsed flip-flops with a low-swing sinusoidal clock has been characterized. The LS-DCCFF has 870 ps longer data to output delay as compared to the full-swing flip-flop at the same setup time for a 100 MHz sinusoidal clock. The functionality of the proposed flip-flop was tested and verified by using the LS-DCCFF in a dual-mode multiply and accumulate (MAC) unit fabricated in TSMC 90-nm CMOS technology. Low-swing resonant clocking achieved around 5.8% reduction in total power with 5.7% area overhead for the MAC.

A VLSI analog computer/math co-processor for a digital computer

A single-chip VLSI analog computer having 80 integrators and 336 other programmable linear and nonlinear circuits is fabricated in a 0.25 /spl mu/m CMOS process. The chip can be used to accelerate a digital computers numerical routines. The IC is 1 cm/sup 2/ and consumes 300 mW.

Dual-edge triggered sense amplifier flip-flop for resonant clock distribution networks

A dual-edge sense amplifier flip-flop (DE-SAFF) for resonant clock distribution networks (CDNs) is proposed. The clocking scheme used to enable dual-edge triggering in the proposed SAFF reduces short circuit power by allowing the precharging transistors to be switched on only for a portion of the clock period. The extracted circuit layout of the proposed DE-SAFF has been simulated in STMicroelectronics 90 nm technology with a resonant clock signal at a frequency of 500 MHz. Simulation results show correct functionality of the flip-flip under process, voltage and temperature variations. Two low-power clocking techniques, the dual-edge triggering method and the emerging resonant (sinusoidal) clocking technique, have been combined to enable further power reduction in the CDN. Modelling the resonant clock distribution system with the proposed flip-flop illustrates that dual-edge triggering can achieve up to 58% reduction in the power consumption of resonant clock networks.

Estimating required driver strength in the resonant clock generator

A detailed analytical approach is proposed to determine the required driver strength in the resonant clock generator. The proposed approach reduces area and power overhead by eliminating the need to have switches with programmable widths and reference pulses with programmable duty cycles. Simulation results show accurate estimation of the required driver strength at short pulse widths. However, as the pulse width increase, accuracy reduces due to overestimation of the transistor driving capability.

A low power Transimpedance Amplifier using inductive feedback approach in 90nm CMOS

An inductive feedback approach for BW extension of Transimpedance Amplifiers has been proposed. The effect of parasitic capacitances of the MOS transistor has been reduced using this approach. The process of zero-pole cancellation to extend the BW of the amplifier has been explained. To demonstrate the feasibility of the technique a new transimpedance amplifier has been simulated in a well-known CMOS technology (i.e. 90nm STMicroelectronics). It achieves a 3-dB bandwidth of more than 16GHz in the presence of a 150fF photodiode capacitance and 5fF loading capacitance while only dissipating 2.2mW. Despite this low power dissipation, the amplifier shows superior noise performance.

Continuous-time DSPs, analog/digital computers and other mixed-domain circuits

This paper reviews our recent research, involving circuits and systems which mix domains traditionally kept separate. Several examples are given, including continuous-time digital signal processors and mixed analog/digital computers. It is argued that by mixing domains one can have advantages which would not otherwise be possible.

Dual-edge triggered energy recovery DCCER flip-flop for low energy applications

Resonant clocking techniques have been shown to achieve significant power reduction compared to square wave clocking. In this paper, we propose a dual-edge triggered Differential Conditional Capturing Energy Recovery (DE-DCCER) flip-flop that allows the clock frequency to be reduced by a factor of two. The proposed flip-flop was tested using STMicroelectronics 90nm process technology. Simulation results show the correct operation of the dual-edge triggered flip-flop at a frequency of 250MHz. Modeling the entire system of the clock distribution network with approximately 10,000 flip-flops shows that dual-edge triggering achieves a 56% power reduction in the clock tree and up to 21% total power reduction for the entire system with a penalty of 36.8% increase in area.

Skew compensation in energy recovery clock distribution networks

In this paper a new approach for skew compensation in energy recovery clock distribution networks is introduced by manipulating the operating speed of the flip-flops. Three types of flip-flops: ¿fast¿, ¿standard¿, and ¿slow¿ are used. Distributing flip-flops according to their delay requirements would reduce the effect of the clocks skew on the outputs of sequentially adjacent flip-flops. This approach increases the skew bounds required by algorithms to balance the skew in the clock distribution network leading to reduced design complexity. Theoretical analysis and simulation results at a clock frequency of 500 MHz show that this approach is feasible and effective where a skew of up to 6.2% of the clock period can be compensated for.

A novel approach for skew compensation in energy recovery clock distribution networks

In this paper a new approach for skew compensation in energy recovery clock distribution networks is introduced by manipulating the operating speed of the flip-flops. Three types of flip-flops: ?fast?, ?standard?, and ?slow? are used. Distributing flip-flops according to their delay requirements would reduce the effect of the clocks skew on the outputs of sequentially adjacent flip-flops. This approach increases the skew bounds required by algorithms to balance the skew in the clock distribution network leading to reduced design complexity. Theoretical analysis and simulation results at a clock frequency of 500 MHz show that this approach is feasible and effective where a skew of up to 6.2% of the clock period can be compensated for.