GoangSeog Choi

Intelligent sensor node based a low power ECG monitoring system

This paper presents a novel two-tier low power electrocardiogram (ECG) monitoring system which consists of a sensor nodes layer and a base station layer by employing a simple but effective Euclidean distance model. To save transmission power, a sensor node only transmits sensed data to a base station when the sensed data shows abnormality. For the low power implementation of the abnormality detection on a local power-hungry sensor node, we propose light-weight computation of Euclidean distance between a sensed ECG signal and a reference ECG signal. Experimental results show that the proposed scheme can reduce power consumption by 39-57% of the sensor nodes and accordingly prolongs the lifetime of the whole monitoring system.

Reconfigurable Front-End System for BD/DVD/CD Recorder

This paper introduces a reconfigurable front-end system that consists of a RF chip and two data processors (DPs). The system has the capability of reading BD/DVD/CDs and recording BD/DVDs. It can be implemented with a RF chip and a BD DP for BD mode and a RF chip and a DVD/CD DP for DVD/CD mode. The newly developed RF chip can process CD, DVD and BD. The presented BD DP can access the BD-R/ROM/RE at 2x speed. The adaptive partial response maximum likelihood (PRML) and optimum power control (OPC) algorithms for improving play ability and recordability of BDs are developed. Due to the proposed adaptive PRML, less than 2 times 10-4 of bit error rate (BER) is achieved with the tilt margin of ±0.6°. The presented OPC algorithm can reduce to the power errors of less than 3 percent in 3 seconds. The developed reconfigurable front-end system is fully verified with real BD/DVD/CDs. Three main chipset of front-end system is fabricated. A RF chip is fabricated in 0.65μm Bi-CMOS process technology and two DPs are fabricated in 0.18μm CMOS process technology.

Analysis and Optimization of Four-Coil Planar Magnetically Coupled Printed Spiral Resonators

High-efficiency power transfer at a long distance can be efficiently established using resonance-based wireless techniques. In contrast to the conventional two-coil-based inductive links, this paper presents a magnetically coupled fully planar four-coil printed spiral resonator-based wireless power-transfer system that compensates the adverse effect of low coupling and improves efficiency by using high quality-factor coils. A conformal architecture is adopted to reduce the transmitter and receiver sizes. Both square architecture and circular architectures are analyzed and optimized to provide maximum efficiency at a certain operating distance. Furthermore, their performance is compared on the basis of the power-transfer efficiency and power delivered to the load. Square resonators can produce higher measured power-transfer efficiency (79.8%) than circular resonators (78.43%) when the distance between the transmitter and receiver coils is 10 mm of air medium at a resonant frequency of 13.56 MHz. On the other hand, circular coils can deliver higher power (443.5 mW) to the load than the square coils (396 mW) under the same medium properties. The performance of the proposed structures is investigated by simulation using a three-layer human-tissue medium and by experimentation.

Power and area-optimised Carry-Select Adder architecture for standard cell-based design

A Carry-Select Adder (CSA) is one of the most suitable adders for high-speed applications, but the power and area penalties are greater, because it requires a double Ripple-Carry Adder (RCA) structure corresponding to carry inputs 0 and 1. Current low-power and low-area techniques are not suitable for a standard cell-based design which is one of the widely adopted design methodologies. Our work proposes two simple optimised architectures suitable for standard cell-based designs. A simple decision logic that replaces the RCA for Carry input 1 in a conventional CSA is proposed. One of the proposed architectures reduces power and area significantly with a small delay penalty compared to the existing techniques. Another proposed architecture improves the speed of operation and reduces the power and area considerably. The first one is more suitable for high-speed arithmetic in battery-operated applications where there is a trade-off between speed and power, while the other one is suitable for high-performance applications which also require area and power optimisation. The proposed architectures were implemented in TSMC 0.18um CMOS technology, and compared with conventional Square Root Carry-Select Adders and an existing standard cell-based design.

Response of transport triggered architectures for high-speed processor design

This paper reports the result of a comparison between reduced instruction set computing and the transport triggered architecture. Because of the simplicity and efficiency of the transport triggered architecture, its processor requires less execution cycles compared to the OpenRisc processor. This paper also presents a case study about designing an Architecture Definition File for a transport triggered architecture-based design tool, and it depicts how the Architecture Definition File structures are responsible for implementing high-speed design. In a custom Architecture Definition File, a new function unit is designed to improve processor performance, and it shows that the cycle count required to implement the Cyclic Redundancy Check algorithm drops to 7 executions from 5031.

Implementation of Indoor Location Tracking System Using ETOA Algorithm in Non-Line-Of-Sight Environment

Many indoor location tracking technologies have been proposed. Generally indoor location tracking using TOA signal is used, there is a weak point that it`s difficult to track the location due to obstacles like a refraction, reflection and dispersion of radio wave. In this paper, we apply ETOA(Estimated-TOA) algorithm in NLOS(Non-Line-Of-Sight) environment to solve above problem. In NLOS environment, TOA value between Beacon and Mobile node is predicted by ETOA algorithm and the tracking of indoor location is also possible to identify using two NLOS beacons of three beacons by this algorithm. We show that the proposed algorithm is accurate location tracking is accomplished using the applying the proposed algorithm to indoor moving robot and the inertia sensor of robot and Kalman filter algorithm.

Performance Evaluation of ECG Compression Algorithms using Classification of Signals based PQSRT Wave Features

An ECG(Electrocardiogram) compression can increase the processing speed of system as well as reduce amount of signal transmission and data storage of long-term records. Whereas conventional performance evaluations of loss or lossless compression algorithms measure PRD(Percent RMS Difference) and CR(Compression Ratio) in the viewpoint of engineers, this paper focused on the performance evaluations of compression algorithms in the viewpoint of diagnostician who diagnosis ECG. Generally, for not effecting the diagnosis in the ECG compression, the position, length, amplitude and waveform of the restored signal of PQRST wave should not be damaged. AZTEC, a typical ECG compression algorithm, is validated its effectiveness in conventional performance evaluation. In this paper, we propose novel performance evaluation of AZTEC in the viewpoint of diagnostician.

Single front-end SOC for accessing CD/DVD/BD with maximum speed

A single front-end SOC with the capability to access all kinds of optical disc is presented. It has the capability to process CD/DVD/BD with maximum speed. It contains an analog front end (AFE), partial response maximum likelihood (PRML) detector, servo-control block, buffer control block etc. It also has numerous analog cores such as analog-to-digital converter (ADC) and phase locked loop (PLL) and digital macros such as digital signal processor (DSP), ARM microprocessor and memories. The presented SOC parallelizes the embedded blocks with the divided channel frequency to enable maximum speed access. It contains 32 million transistors in a 63 mm2 die, and is fabricated with 0.13 mum CMOS technology. It has a channel frequency of 530 MHz and a power consumption of 1.1 W at BD 1x speed. It was fully verified with CD/DVD/BD with maximum speed.

A current mode equalizer for an optical disc front-end

A 1.2 V current-mode 7th-order Bessel low pass filter (LPF) with programmable boosting gain for an optical disc front-end is presented. The wide cut-off frequency tuning is achieved by using current-mode buffers, triode region MOS resistors and varactors. The constant gm biasing and the current-mode oscillator ensure that frequency characteristics are robust to process, voltage and temperature variations. It covers a wide frequency tuning range of 1-140 MHz and speeds of CD 4x - BD 8x, for CD/DVD/BD. It has a low power consumption of 19 mW and a small size of 0.167 mm2, and is fabricated with 0.13 mum CMOS technology.

Design and implementation of a novel LT codec architecture on TTA based codesign environment

The main aim of this paper is to explain the generation technique of application specific function units (FUs) for reducing the number of instructions in Luby Transform (LT) codec processor. For this reason, Transport Triggered Architecture (TTA) is taken as an active processor template for designing a high-speed TTA-based LT codec processor using TTA-based Co-design Environment (TCE) tool. In this design, processor architectures named as P1, P2, P3, P4, P5, and P6 are generated to gradually improve the performance of the TTA processor. P6 took only 4,466 cycles and 43ms to simulate an LT codec system. In this paper, P6 of the TCE tool took only a single iteration to generate the decoded signal.