Hyun-jeong Park

A 0.18 /spl mu/m CMOS front-end processor for a blu-ray disc recorder with an adaptive PRML

A single-chip front-end SoC, comprising a PRML with an adaptive equalizer, a data processor including a modem and error-correcting code and digital servo with a 16 b DSP, is for Blu-ray disc application. The chip dissipates 0.9 W at 1.8 V and 132 MHz, contains 12M transistors and occupies 50 mm/sup 2/ in 0.18 /spl mu/m CMOS technology.

A 833 Mb/s 2.5 V 4 Mb double data rate SRAM

A double-data-rate (DDR) SRAM overcomes the limitation of a single-data-rate (SDR) SRAM. The main features are an auto-tracking bitline scheme to reduce core cycle time, a shortened main data line for current reduction, a noise immune circuit having high-speed transfer characteristics through a dual-rail reset dynamic circuit, a two bit pre-fetched operation, and strobe clocks synchronized with the output data to guarantee CPU data-validation time.

A 0.18 /spl mu/m CMOS SoC of a front-end hardware platform for DVD-multi recorders

This work presents a 0.18 /spl mu/m CMOS system on a chip (SoC) that is a hardware platform for the front-end of DVD-multi recorders (FESOC). It has one 32 bit RISC CPU and one 16 bit DSP as well as most of the necessary components for DVD recorders, except for an analog front end (AFE) and some memories. The necessary building blocks are a partial response channel maximum likelihood detector (PRML), a servo signal processor (SERVO), write strategy controller (WSC), a data processor (DP), an AT-attachment packet interface (ATAPI), and a micro computer unit (MCU). Using a three-layered bus architecture enables this FESOC to work well with a 16 bit-wide bus at 67 MHz for 8/spl times/ DVD operation, and to be implemented with a short development time. The FESOC is fabricated in 0.18 /spl mu/m 1-poly 5-metal CMOS technology. It contains 8.4 million transistors in a 46 mm/sup 2/ die and consumes 1.4 W with a channel clock of 209.28 MHz in 8/spl times/ operation mode.

Reconfigurable Front-End System for BD/DVD/CD Recorder

This paper introduces a reconfigurable front-end system that consists of a RF chip and two data processors (DPs). The system has the capability of reading BD/DVD/CDs and recording BD/DVDs. It can be implemented with a RF chip and a BD DP for BD mode and a RF chip and a DVD/CD DP for DVD/CD mode. The newly developed RF chip can process CD, DVD and BD. The presented BD DP can access the BD-R/ROM/RE at 2x speed. The adaptive partial response maximum likelihood (PRML) and optimum power control (OPC) algorithms for improving play ability and recordability of BDs are developed. Due to the proposed adaptive PRML, less than 2 times 10-4 of bit error rate (BER) is achieved with the tilt margin of ±0.6°. The presented OPC algorithm can reduce to the power errors of less than 3 percent in 3 seconds. The developed reconfigurable front-end system is fully verified with real BD/DVD/CDs. Three main chipset of front-end system is fabricated. A RF chip is fabricated in 0.65μm Bi-CMOS process technology and two DPs are fabricated in 0.18μm CMOS process technology.