Godefridus Adrianus Maria Hurkx

Intentionally Carbon-Doped AlGaN/GaN HEMTs: Necessity for Vertical Leakage Paths

Dynamic on-resistance (RON) in heavily carbon-doped AlGaN/GaN high electron mobility transistors is shown to be associated with the semi-insulating carbon-doped buffer region. Using transient substrate bias, differences in RON dispersion between transistors fabricated on nominally identical epilayer structures were found to be due to the band-to-band leakage resistance between the buffer and the 2-DEG. Contrary to normal expectations, suppression of dynamic RON dispersion in these devices requires a high density of active defects to increase reverse leakage current through the depletion region allowing the floating weakly p-type buffer to remain in equilibrium with the 2-DEG.

Impact of Donor Traps on the 2DEG and Electrical Behavior of AlGaN/GaN MISFETs

As an important step in understanding trap-related mechanisms in AlGaN/GaN transistors, the physical properties of surface states have been analyzed through the study of the transfer characteristics of a MISFET. This letter focused initially on the relationship between donor parameters (concentration and energy level) and electron density in the channel in AlGaN/GaN heterostructures. This analysis was then correlated to dc and pulsed measurements of the transfer characteristics of a MISFET, where the gate bias was found to modulate either the channel density or the donor states. Traps-free and traps-frozen TCAD simulations were performed on an equivalent device to capture the donor behavior. A donor concentration of 1.14×1013 cm-2 with an energy level located 0.2 eV below the conduction band edge gave the best fit to measurements. With the approach described here, we were able to analyze the region of the MISFET that corresponds to the drift region of a conventional HEMT.

OFF-State Degradation of AlGaN/GaN Power HEMTs: Experimental Demonstration of Time-Dependent Drain-Source Breakdown

This paper reports the experimental demonstration of a novel degradation mechanism of high-power AlGaN/GaN high electron mobility transistors (HEMTs), that is, time-dependent drain-source breakdown. With current-controlled breakdown measurements and constant voltage stress experiments we demonstrate that: 1) when submitted to constant voltage stress, in the OFF-state, the HEMTs can show a significant degradation; 2) the degradation process is time-dependent, and consists of a measurable increase in subthreshold drain-source leakage; this effect is ascribed to the accumulation of positive charge in proximity of the gate, consistently with previous theoretical calculations; and 3) a catastrophic (and permanent) failure is observed for long stress times, possibly due to thermal runaway or to the increase in the electric field in proximity of the localized drain-source leakage paths.

Impact of the backside potential on the current collapse of GaN SBDs and HEMTs

This paper shows both experimentally and in simulation that the amount of current collapse for GaN SBDs and HEMTs strongly depends on the node to which the backside is connected, i.e, how the device is packaged, and the underlying physics is explained. It is shown that the difference in current collapse is not due to a difference in charge trapping. The reduction in current collapse for a backside-to-anode/source connection is due to a compensating switching charge that is not present when the backside is connected to the cathode/drain, for which stronger current collapse is observed.

Field-Related Failure of GaN-on-Si HEMTs: Dependence on Device Geometry and Passivation

This paper reports on an extensive analysis of the breakdown of GaN-based Schottky-gated HEMTs submitted to high-voltage stress. The analysis was carried out on transistors with different lengths of the drain-side gatehead (LGH), corresponding to different levels of electric field across the SiN passivation. Based on dc measurements, 2-D simulations, and optical analysis, we demonstrate the following original results: 1) when submitted to high drain voltages (in the OFF-state), the transistors can show catastrophic failure; 2) electroluminescence microscopy indicates the presence of hot-spots on the drain-side of the gate; 2-D simulations support the hypothesis that failure occurs in correspondence of the gate-head, on the drainside edge, where the electric field in the silicon nitride passivation has its maximum; 3) this hypothesis is confirmed by the results of transmission electron microscope failure analysis that demonstrate the generation of a leakage path between the gate metal and the channel, 4) and by the dependence of the destructive voltage on the LGH value. 5) in addition, we propose and demonstrate an approach for improving the reliability of the devices, i.e., using a graded SiN passivation with increased thickness. The results described in this paper provide important information for the device optimization of Schottky-gated HEMTs.

Quantitative characterization of the trapped charge profile in GaN HEMTs by sense nodes in the drain-extension region

A new methodology is presented that directly extracts the location and amount of trapped charge in GaN HEMTs by making use of a special test structure with an additional sense node in-between the gate and drain. The technique is validated on three wafer types: one for which trapping predominantly occurs in the GaN epitaxy, one with both epitaxy trapping and surface charge injection, and one for our optimized 650-V GaN technology, for which charge trapping is almost completely eliminated.

A Quantum–Mechanical View on the Capacitance of a Silicon p-n Junction

We have calculated the capacitance of a silicon p-n junction from a self-consistent solution to the effective-mass Schroumldinger and Poisson equations. Although the p-n product and the charge distribution deviate strongly from the semiclassical calculations, the quantum mechanically calculated capacitance of the silicon p-n junction differs only weakly from the semiclassical result. We show that the deviation from the semiclassical result can be approximated as band-gap narrowing in the quasi-neutral regions due to the exchange-energy term in the effective-mass Schroumldinger equation

Semiconductor heterojunction device

This paper reviews the rationale for the use of heterojunctions in devices. Through the use of specific examples, the physical properties of this powerful technique are demonstrated. Comparisons of common epitaxial growth techniques suitable for heterojunction growths are given. Introduction The demonstration of GaAs /GaAlAs semiconductor lasers in the 1970s in which the use of the GaAs /GaAlAs heterojunction provided the key technology improvement to achieve CW room temperature operation, has provided the impetus for both epitaxial material growth techniques and new device structures that has led to a proliferation of devices in III -V, IV -VI and II -VI semiconductor compounds. These devices attempt to exploit powerful physical properties caused by changes in the band structure or index of refraction due to the presence of heterostructures. The purpose of this article is to review the rationale for heterostructures and, through the use of examples, demonstrate the different physical mechanisms that can be exploited in heterojunction devices. The examples used in this article are by no means an extensive list and, moreover, are used to stimulate imaginative device physicists to exploit heterostructures in even more powerful ways. The reasons heterostructures are employed can be summarized as: to confine electrical carriers to provide physical (spatial) carrier separation to confine optical fields to provide separate optical /electrical regions In order to demonstrate these effects, the following examples will be shown: 1. Laser carrier confinement optical confinement 2. Detectors separate optical /electrical regions 3. High electron mobility transistors spatial carrier separation confine electrical carriers 4. Heterojunction bipolar transistors confine electrical carriers 5. Heterojunction CCDs separate optical /electrical regions Material techniques Figure 1 shows a schematic of a simple heterojunction device. Notice that the heterojunction occurs where the two different materials (e.g. GaAs /A1GaAs) meet. The interface of the junction is critical to eventual device performance. The interface must be established in such a manner that the crystalline perfection of the single crystal semiconductor is maintained. This usually (but not always) requires that the lattice size of the material on each side of the junction be nearly identical. Large (or in some cases even small) lattice mismatches result in large defect densities, traps, dislocations and 7 in devi technique are e /GaAlAs semiconductor i the use /GaAlAs heterojunction provided the key technology improvement to achieve CW 1, has provided he growth structures that has led to a proliferation of devices in III-V -VI and II-VI semiconductor p o index of refraction due to t th ratio the different physical in heterojunc devi a us to stimulate imaginative i po wa sum as (sp ca separati separate optical fo e be show