Jan Sonsky

Intentionally Carbon-Doped AlGaN/GaN HEMTs: Necessity for Vertical Leakage Paths

Dynamic on-resistance (RON) in heavily carbon-doped AlGaN/GaN high electron mobility transistors is shown to be associated with the semi-insulating carbon-doped buffer region. Using transient substrate bias, differences in RON dispersion between transistors fabricated on nominally identical epilayer structures were found to be due to the band-to-band leakage resistance between the buffer and the 2-DEG. Contrary to normal expectations, suppression of dynamic RON dispersion in these devices requires a high density of active defects to increase reverse leakage current through the depletion region allowing the floating weakly p-type buffer to remain in equilibrium with the 2-DEG.

Extensive Investigation of Time-Dependent Breakdown of GaN-HEMTs Submitted to OFF-State Stress

This paper reports the experimental demonstration of time-dependent dielectric breakdown in GaN-based high-electron mobility transistors (HEMTs) submitted to OFF-state stress. Based on combined breakdown measurements, constant voltage stress tests, and 2-D simulations, we demonstrate the following relevant results. First, GaN-based HEMTs with a breakdown voltage higher than 1000 V (evaluated by dc measurements) may show time-dependent failure when exposed to OFF-state stress with VDS in the range 600-700 V. Second, time-to-failure (TTF) is Weibull-distributed, and has an exponential dependence on the stress voltage level. Third, time-dependent breakdown is ascribed to the failure of the SiN dielectric at the edge of the gate overhang, on the drain side. Fourth, 2-D simulations confirm that-in this region-the electric field exceeds 6 MV/cm, i.e., the dielectric strength of SiN. Finally, we demonstrate that by limiting the electric field in the nitride through epitaxy and process improvements, it is possible to increase the TTF by three orders of magnitude.

Impact of Donor Traps on the 2DEG and Electrical Behavior of AlGaN/GaN MISFETs

As an important step in understanding trap-related mechanisms in AlGaN/GaN transistors, the physical properties of surface states have been analyzed through the study of the transfer characteristics of a MISFET. This letter focused initially on the relationship between donor parameters (concentration and energy level) and electron density in the channel in AlGaN/GaN heterostructures. This analysis was then correlated to dc and pulsed measurements of the transfer characteristics of a MISFET, where the gate bias was found to modulate either the channel density or the donor states. Traps-free and traps-frozen TCAD simulations were performed on an equivalent device to capture the donor behavior. A donor concentration of 1.14×1013 cm-2 with an energy level located 0.2 eV below the conduction band edge gave the best fit to measurements. With the approach described here, we were able to analyze the region of the MISFET that corresponds to the drift region of a conventional HEMT.

OFF-State Degradation of AlGaN/GaN Power HEMTs: Experimental Demonstration of Time-Dependent Drain-Source Breakdown

This paper reports the experimental demonstration of a novel degradation mechanism of high-power AlGaN/GaN high electron mobility transistors (HEMTs), that is, time-dependent drain-source breakdown. With current-controlled breakdown measurements and constant voltage stress experiments we demonstrate that: 1) when submitted to constant voltage stress, in the OFF-state, the HEMTs can show a significant degradation; 2) the degradation process is time-dependent, and consists of a measurable increase in subthreshold drain-source leakage; this effect is ascribed to the accumulation of positive charge in proximity of the gate, consistently with previous theoretical calculations; and 3) a catastrophic (and permanent) failure is observed for long stress times, possibly due to thermal runaway or to the increase in the electric field in proximity of the localized drain-source leakage paths.

Impact of the backside potential on the current collapse of GaN SBDs and HEMTs

This paper shows both experimentally and in simulation that the amount of current collapse for GaN SBDs and HEMTs strongly depends on the node to which the backside is connected, i.e, how the device is packaged, and the underlying physics is explained. It is shown that the difference in current collapse is not due to a difference in charge trapping. The reduction in current collapse for a backside-to-anode/source connection is due to a compensating switching charge that is not present when the backside is connected to the cathode/drain, for which stronger current collapse is observed.

Ultra-flexible, layout-enabled field plates for HV transistor integration in SOI-based CMOS

Field plates are commonly used to enhance the performance of high voltage devices and to improve the trade-off between breakdown voltage and specific on-resistance, but they typically require dedicated extra process steps. This paper presents a novel concept of field plate implementation in baseline SOI-CMOS by means of a smart layout without extra processing steps. Such layout-enabled field plates are experimentally demonstrated in a 130 nm SOI-CMOS process, showing a breakdown voltage up to 60 V (3-4x improvement compared to a traditional extended-drain MOSFET). These layout-enabled field plates allow an ultimate flexibility in device optimization, e.g. for multiple voltage domains, robust safe-operating-area and high-frequency power switching.

The dynamics of surface donor traps in AlGaN/GaN MISFETs using transient measurements and TCAD modelling

This paper presents a detailed and correlated (i) Id-Vg, (ii) Cgg-Vg, and (iii) transient analysis of donor traps in a SiN/GaN/AlGaN/GaN Metal-Insulator-Semiconductor Field-Effect Transistor (MISFET) fabricated on a silicon substrate. We explain for the first time that the long-time constants are due to the close coupling between the emission/capture processes on one hand and the transient transport of electrons across the GaN/AlGaN barrier on the other. Emission and capture time constants were extracted for several bias conditions and temperatures. Moreover, we have developed a TCAD model that consistently gives a good match to DC, AC, and transient experimental results.

Local buried oxide technology for HV transistors integrated in CMOS

Automotive applications require full dielectric isolation of the high voltage and analog components. Such isolation is typically realized by BCD technologies built on SOI. The drawbacks of using SOI wafers, i.e. deviation from the baseline bulk CMOS and increased overall cost, can be addressed by manufacturing local SOI islands in the standard bulk wafer. This paper presents a method to manufacture a local buried oxide using LoBOX technology and its integration to baseline CMOS. Our LoBOX technology is based on a sacrificial SiGe layer buried in bulk substrate and subsequently replaced with oxide. It is a general isolation solution that allows flexible local SOI and local BOX thickness. We have integrated our LoBOX technology in a 130 nm bulk CMOS process to demonstrate its feasibility. The manufactured HV transistors isolated with local BOX, feature almost identical performance as those manufactured on commercial SOI wafers.

Field-Related Failure of GaN-on-Si HEMTs: Dependence on Device Geometry and Passivation

This paper reports on an extensive analysis of the breakdown of GaN-based Schottky-gated HEMTs submitted to high-voltage stress. The analysis was carried out on transistors with different lengths of the drain-side gatehead (LGH), corresponding to different levels of electric field across the SiN passivation. Based on dc measurements, 2-D simulations, and optical analysis, we demonstrate the following original results: 1) when submitted to high drain voltages (in the OFF-state), the transistors can show catastrophic failure; 2) electroluminescence microscopy indicates the presence of hot-spots on the drain-side of the gate; 2-D simulations support the hypothesis that failure occurs in correspondence of the gate-head, on the drainside edge, where the electric field in the silicon nitride passivation has its maximum; 3) this hypothesis is confirmed by the results of transmission electron microscope failure analysis that demonstrate the generation of a leakage path between the gate metal and the channel, 4) and by the dependence of the destructive voltage on the LGH value. 5) in addition, we propose and demonstrate an approach for improving the reliability of the devices, i.e., using a graded SiN passivation with increased thickness. The results described in this paper provide important information for the device optimization of Schottky-gated HEMTs.

Impact of Silicon Nitride Stoichiometry on the Effectiveness of AlGaN/GaN HEMT Field Plates

Field plate (FP) control of current collapse and channel electric field distribution in AlGaN/GaN High Electron Mobility Transistors is investigated as a function of low-pressure chemical vapor deposition silicon-nitride stoichiometry. Dependence of current collapse is seen, however, this also leads to enhanced FP pinchoff voltages and higher leakage. Electric field concentration at the gate edge is indicated by measuring OFF-state Two dimensional electron gas position with a sense contact technique. A model explaining the FP threshold variation due to barrier leakage is proposed.